• Physical Function Configuration Register Set
    • Vendor ID and Device ID @0x0
    • Command and Status Register @0x4
    • Revision ID and Class Code Register @0x8
    • BIST, Header Type, Latency Timer and Cache Line Size Registers @0xc
    • Base Address Register 0 @0x10
    • Base Address Register 1 @0x14
    • Base Address Register 2 @0x18
    • Base Address Register 3 @0x1c
    • Base Address Register 4 @0x20
    • Base Address Register 5 @0x24
    • Reserved @0x28
    • Subsystem Vendor ID and Subsystem ID Register @0x2c
    • Expansion ROM Base Address Register @0x30
    • Capabilities Pointer @0x34
    • Reserved @0x38
    • Interrupt Line and Interrupt Pin Register @0x3c
    • Reserved @0x40 + [0..15 * 0x4]
    • Power Management Capabilities Register @0x80
    • Power Management Control/Status Report @0x84
    • Reserved @0x88 + [0..1 * 0x4]
    • MSI Control Register @0x90
    • MSI Message Low Address Register @0x94
    • MSI Message High Address Register @0x98
    • MSI Message Data Register @0x9c
    • MSI Mask Register @0xa0
    • MSI Pending Bits Register @0xa4
    • Reserved @0xa8 + [0..1 * 0x4]
    • MSI-X Control Register @0xb0
    • MSI-X Table Offset Register @0xb4
    • MSI-X Pending Interrupt Register @0xb8
    • Reserved @0xbc Reserved
    • PCI Express Capability List Register @0xc0
    • PCI Express Device Capabilities Register @0xc4
    • PCI Express Device Control and Status Register @0xc8
    • Link Capabilities Register @0xcc
    • Link Control and Status Register @0xd0
    • Reserved @0xd4
    • Reserved @0xd8
    • Reserved @0xdc + [0..1 * 0x4]
    • PCI Express Device Capabilities Register 2 @0xe4
    • PCI Express Device Control and Status Register 2 @0xe8
    • Link Capabilities Register 2 @0xec
    • Link Control and Status Register 2 @0xf0
    • Reserved @0xf4 + [0..2 * 0x4]
    • Advanced Error Reporting (AER) Enhanced Capability Header Register @0x100
    • Uncorrectable Error Status Register @0x104
    • Uncorrectable Error Mask Register @0x108
    • Uncorrectable Error Severity Register @0x10c
    • Correctable Error Status Register @0x110
    • Correctable Error Mask Register @0x114
    • Advanced Error Capabilities and Control Register @0x118
    • Header Log Register 0 @0x11c
    • Header Log Register 1 @0x120
    • Header Log Register 2 @0x124
    • Header Log Register 3 @0x128
    • Reserved @0x12c + [0..2 * 0x4]
    • TLP Prefix Log Register 0 @0x138
    • TLP Prefix Log Register 1 @0x13c
    • ARI Extended Capability Header Register @0x140
    • ARI Capability Register and ARI Control Register @0x144
    • Reserved @0x148 + [0..1 * 0x4]
    • Device Serial Number Capability Header Register @0x150
    • Device Serial Number Register 0 @0x154
    • Device Serial Number Register 1 @0x158
    • Reserved @0x15c
    • Power Budgeting Enhanced Capability Header @0x160
    • Power Budgeting Data Select Register @0x164
    • Power Budgeting Data Register @0x168
    • Power Budget Capability Register @0x16c
    • Reserved @0x170 + [0..3 * 0x4]
    • Resizable BAR Extended Capability Header Register @0x180
    • Resizable BAR Capability Register 0 @0x184
    • Resizable BAR Control Register 0 @0x188
    • Resizable BAR Capability Register 1 @0x18c
    • Resizable BAR Control Register 1 @0x190
    • Resizable BAR Capability Register 2 @0x194
    • Resizable BAR Control Register 2 @0x198
    • Resizable BAR Capability Register 3 @0x19c
    • Resizable BAR Control Register 3 @0x1a0
    • Resizable BAR Capability Register 4 @0x1a4
    • Resizable BAR Control Register 4 @0x1a8
    • Resizable BAR Capability Register 5 @0x1ac
    • Resizable BAR Control Register 5 @0x1b0
    • Latency Tolerance Reporting (LTR) Extended Capability Header Register @0x1b8
    • LTR Max Snoop/Max No-Snoop Latency Register @0x1bc
    • DPA Extended Capability Header Register @0x1c0
    • DPA Capability Register @0x1c4
    • DPA Latency Indicator Register @0x1c8
    • DPA Control and Status Registers @0x1cc
    • Dynamic Power Allocation Array Register 0 @0x1d0
    • Dynamic Power Allocation Array Register 1 @0x1d4
    • SR-IOV Extended Capability Header Register @0x200
    • SR-IOV Capabilities Register @0x204
    • SR-IOV Control and Status Registers @0x208
    • Initial VFs/Total VFs Register @0x20c
    • Function Dependency Link/NumVFs Register @0x210
    • VF Offset/Stride Register @0x214
    • VF Device ID Register @0x218
    • Supported Page Sizes Register @0x21c
    • System Page Size Register @0x220
    • VF Base Address Register 0 @0x224
    • VF Base Address Register 1 @0x228
    • VF Base Address Register 2 @0x22c
    • VF Base Address Register 3 @0x230
    • VF Base Address Register 4 @0x234
    • VF Base Address Register 5 @0x238
    • VF Migration State Array Offset Register Address @0x23c
    • TPH Requester Extended Capability Header Register @0x274
    • TPH Requester Capability Register @0x278
    • TPH Requester Control Register @0x27c
    • TPH ST Table @0x280
    • TPH ST Table @0x284
    • TPH ST Table @0x288
    • TPH ST Table @0x28c
    • Secondary PCI Express Extended Capability Header Register @0x300
    • Link Control3 Register @0x304
    • Lane Error Status Register @0x308
    • Lane Equalization Control Register 0 @0x30c
    • Lane Equalization Control Register 1 @0x310
    • Vendor Specific Extended Capability Header @0x400
    • Vendor Specific Header Register @0x404
    • Vendor Specific Control Register @0x408
    • Vendor Specific Data Register 0 @0x40c
    • PASID Extended Capability Header @0x440
    • PASID Capability Header @0x444
    • ATS Capability Header Register @0x5c0
    • ATS Capability Control Register @0x5c4
    • ATS Page Request Capability Header Register @0x640
    • ATS Page Request Control Status Register @0x644
    • ATS Outstanding Page Request Capacity Register @0x648
    • ATS Outstanding Page Request Allocation @0x64c
    • L1 PM Substates Extended Capability Header Register @0x900
    • L1 PM Substates Capabilities Register @0x904
    • L1 PM Substates Control 1 Register @0x908
    • L1 PM Substates Control 2 Register @0x90c
    • DL Feature Extended Capability Header Register @0x910
    • DL Feature Capabilities Register @0x914
    • DL Feature Status Register @0x918
    • Margining Extended Capability Header Register @0x920
    • Margining Port Capabilities and Status Register @0x924
    • Margining Lane Control and Status Register for Lane 0 @0x928
    • Margining Lane Control and Status Register for Lane 1 @0x92c
    • Margining Lane Control and Status Register for Lane 2 @0x930
    • Margining Lane Control and Status Register for Lane 3 @0x934
    • Physical Layer 16 GT/s Extended Capability Header Register @0x9c0
    • Physical Layer 16GTs Status Register @0x9cc
    • Physical Layer 16GTs Local Data Parity Mismatch Status Register @0x9d0
    • Physical Layer 16GTs First Retimer Data Parity Mismatch Status Register @0x9d4
    • Physical Layer 16GTs Second Retimer Data Parity Mismatch Status Register @0x9d8
    • Physical Layer 16GTs Reserved Register @0x9dc
    • 16 GT/s Lane Equalization Control Register 0 @0x9e0
  • Virtual Function Configuration Register Set
    • Vendor ID and Device ID @0x0
    • Command and Status Register @0x4
    • Revision ID and Class Code Register @0x8
    • BIST, Header Type, Latency Timer and Cache Line Size Registers @0xc
    • Base Address Register 0 @0x10
    • Base Address Register 1 @0x14
    • Base Address Register 2 @0x18
    • Base Address Register 3 @0x1c
    • Base Address Register 4 @0x20
    • Base Address Register 5 @0x24
    • Subsystem Vendor ID and Subsystem ID Register @0x2c
    • Expansion ROM Base Address Register @0x30
    • Capabilities Pointer @0x34
    • Reserved @0x40 + [0..15 * 0x4]
    • Interrupt Line and Interrupt Pin Register @0x3c
    • Power Management Capabilities Register @0x80
    • Power Management Control/Status Report @0x84
    • Reserved @0x88 + [0..1 * 0x4]
    • MSI Control Register @0x90
    • MSI Message Low Address Register @0x94
    • MSI Message High Address Register @0x98
    • MSI Message Data Register @0x9c
    • MSI Mask Register @0xa0
    • MSI Pending Bits Register @0xa4
    • MSI-X Control Register @0xb0
    • MSI-X Table Offset Register @0xb4
    • MSI-X Pending Interrupt Register @0xb8
    • PCI Express Capability List Register @0xc0
    • PCI Express Device Capabilities Register @0xc4
    • PCI Express Device Control and Status Register @0xc8
    • Link Capabilities Register @0xcc
    • PCI Express Device Capabilities Register 2 @0xe4
    • Link Capabilities Register 2 @0xec
    • Advanced Error Reporting (AER) Enhanced Capability Header Register @0x100
    • Uncorrectable Error Status Register @0x104
    • Uncorrectable Error Mask Register @0x108
    • Uncorrectable Error Severity Register @0x10c
    • Correctable Error Status Register @0x110
    • Correctable Error Mask Register @0x114
    • Advanced Error Capabilities and Control Register @0x118
    • Header Log Register 0 @0x11c
    • Header Log Register 1 @0x120
    • Header Log Register 2 @0x124
    • Header Log Register 3 @0x128
    • TLP Prefix Log Register 0 @0x138
    • TLP Prefix Log Register 1 @0x13c
    • ARI Extended Capability Header Register @0x140
    • ARI Capability Register and ARI Control Register @0x144
    • TPH Requester Enhanced Capability Header Register @0x274
    • TPH Requester Capability Register @0x278
    • TPH Requester Control Register @0x27c
    • TPH ST Table @0x280
    • TPH ST Table @0x284
    • TPH ST Table @0x288
    • TPH ST Table @0x28c
    • ATS Capability Header Register @0x5c0
    • ATS Capability Control Register @0x5c4
  • Root Port Configuration Register Set
    • Vendor ID and Device ID @0x0
    • Command and Status Register @0x4
    • Revision ID and Class Code Register @0x8
    • BIST, Header Type, Latency Timer and Cache Line Size Registers @0xc
    • Root Complex Base Address Register 0 @0x10
    • Root Complex Base Address Register 1 @0x14
    • Primary Bus Number, Secondary Bus Number, Subordinate Bus Number, Secondary Latency Timer @0x18
    • I/O Base, I/O Limit, Secondary Status Register @0x1c
    • Memory Base, Memory Limit @0x20
    • Prefetchable Memory Base,Prefetchable Memory Limit @0x24
    • Prefetchable Base Upper @0x28
    • Prefetchable Limit Upper @0x2c
    • I/O Base Upper, I/O Limit Upper @0x30
    • Capabilities Pointer @0x34
    • Expansion ROM Base Address Register @0x38
    • Interrupt Line, Interrupt Pin Register and Bridge Control Register @0x3c
    • Power Management Capabilities Register @0x80
    • Power Management Control/Status Report @0x84
    • MSI Control Register @0x90
    • MSI Message Low Address Register @0x94
    • MSI Message High Address Register @0x98
    • MSI Message Data Register @0x9c
    • MSI Mask Register @0xa0
    • MSI Pending Bits Register @0xa4
    • MSI-X Control Register @0xb0
    • MSI-X Table Offset Register @0xb4
    • MSI-X Pending Interrupt Register @0xb8
    • PCI Express Capability List Register @0xc0
    • PCI Express Device Capabilities Register @0xc4
    • PCI Express Device Control and Status Register @0xc8
    • Link Capabilities Register @0xcc
    • Link Control and Status Register @0xd0
    • Slot Capability Register @0xd4
    • Slot Control and Status Register @0xd8
    • Root Control and Capability Register @0xdc
    • Root Status Register @0xe0
    • PCI Express Device Capabilities 2 Register @0xe4
    • PCI Express Device Control and Status 2 Register @0xe8
    • Link Capabilities Register 2 @0xec
    • Link Control and Status 2 Register @0xf0
    • Advanced Error Reporting (AER) Enhanced Capability Header Register @0x100
    • Uncorrectable Error Status Register @0x104
    • Uncorrectable Error Mask Register @0x108
    • Uncorrectable Error Severity Register @0x10c
    • Correctable Error Status Register @0x110
    • Correctable Error Mask Register @0x114
    • Advanced Error Capabilities and Control Register @0x118
    • Header Log Register 0 @0x11c
    • Header Log Register 1 @0x120
    • Header Log Register 2 @0x124
    • Header Log Register 3 @0x128
    • Root Error Command Register @0x12c
    • Root Error Status Register @0x130
    • Error Source Identification Register @0x134
    • TLP Prefix Log Register 0 @0x138
    • Device Serial Number Capability Header Register @0x150
    • Device Serial Number Register 0 @0x154
    • Device Serial Number Register 1 @0x158
    • Secondary PCI Express Extended Capability Header Register @0x300
    • Link Control3 Register @0x304
    • Lane Error Status Register @0x308
    • Lane Equalization Control Register 0 @0x30c
    • Lane Equalization Control Register 1 @0x310
    • L1 PM Substates Extended Capability Header Register @0x900
    • L1 PM Substates Capabilities Register @0x904
    • L1 PM Substates Control 1 Register @0x908
    • L1 PM Substates Control 2 Register @0x90c
    • DL Feature Extended Capability Header Register @0x910
    • DL Feature Capabilities Register @0x914
    • DL Feature Status Register @0x918
    • Margining Extended Capability Header Register @0x920
    • Margining Port Capabilities and Status Register @0x924
    • Margining Lane Control and Status Register for Lane 0 @0x928
    • Margining Lane Control and Status Register for Lane 1 @0x92c
    • Margining Lane Control and Status Register for Lane 2 @0x930
    • Margining Lane Control and Status Register for Lane 3 @0x934
    • Physical Layer 16 GT/s Extended Capability Header Register @0x9c0
    • Physical Layer 16GTs Capabilities Register @0x9c4
    • Physical Layer 16GTs Control Register @0x9c8
    • Physical Layer 16GTs Status Register @0x9cc
    • Physical Layer 16GTs Local Data Parity Mismatch Status Register @0x9d0
    • Physical Layer 16GTs First Retimer Data Parity Mismatch Status Register @0x9d4
    • Physical Layer 16GTs Second Retimer Data Parity Mismatch Status Register @0x9d8
    • Physical Layer 16GTs Reserved Register @0x9dc
    • 16 GT/s Lane Equalization Control Register 0 @0x9e0
  • Local Management Registers
    • Physical Layer Configuration Register 0 @0x0
    • Physical Layer Configuration Register 1 @0x4
    • Data Link Layer Timer Configuration Register @0x8
    • Receive Credit Limit Register 0 VC0 @0xc
    • Receive Credit Limit Register 1 VC0 @0x10
    • Transmit Credit Limit Register 0 VC0 @0x14
    • Transmit Credit Limit Register 1 VC0 @0x18
    • Transmit Credit Update Interval Configuration Register 0 @0x1c
    • Transmit Credit Update Interval Configuration Register 1 @0x20
    • L0S Timeout Limit Register @0x24
    • Transmit TLP Count Register @0x28
    • Transmit TLP Payload Dword Count Register @0x2c
    • Receive TLP Count Register @0x30
    • Receive TLP Payload Dword Count Register @0x34
    • Completion Timeout Limit Register 0 @0x38
    • Completion Timeout Limit Register 1 @0x3c
    • L1 State Re-Entry Delay Register @0x40
    • Vendor ID Register @0x44
    • ASPM L1 Entry Timeout Delay Register @0x48
    • PME TurnOff Ack Delay Register @0x4c
    • Linkwidth Control Register @0x50
    • Physical Layer Configuration Register 2 @0x54
    • SRIS Control Register @0x74
    • Shadow Register Header Log 0 @0x100
    • Shadow Register Header Log 1 @0x104
    • Shadow Register Header Log 2 @0x108
    • Shadow Register Header Log 3 @0x10c
    • Shadow Register Function Number @0x110
    • Shadow Register UR Error @0x114
    • PM_CLK Frequency Register @0x140
    • DL GEN1 Receive DLLP Count Debug Register @0x144
    • DL GEN2 Receive DLLP Count Debug Register @0x148
    • DL GEN3 Receive DLLP Count Debug @0x14c
    • DL GEN4 Receive DLLP Count Debug Register @0x150
    • Vendor Defined Message Tag Register @0x158
    • Negotiated Lane Map Register @0x200
    • Receive FTS Count Register @0x204
    • Debug Mux Control Register @0x208
    • Local Error and Status Register @0x20c
    • Local Interrupt Mask Register @0x210
    • LCRC Error Count Register @0x214
    • ECC Correctable Error Count Register @0x218
    • LTR Snoop/No-Snoop Latency Register @0x21c
    • LTR Message Generation Control Register @0x220
    • PME Service Timeout Delay Register @0x224
    • Root Port Requestor ID Register @0x228
    • Endpoint Bus and Device Number Register @0x22c
    • Debug Mux Control 2 Register @0x234
    • PHY STATUS 1 Register @0x238
    • Debug Mux Control 3 Register @0x23c
    • Physical Function BAR Configuration Register 0 @0x240
    • Physical Function BAR Configuration Register 1 @0x244
    • Physical Function BAR Configuration Register 0 @0x248
    • Physical Function BAR Configuration Register 1 @0x24c
    • Physical Function BAR Configuration Register 0 @0x250
    • Physical Function BAR Configuration Register 1 @0x254
    • Physical Function BAR Configuration Register 0 @0x258
    • Physical Function BAR Configuration Register 1 @0x25c
    • Virtual Function BAR Configuration Register 0 @0x280
    • Virtual Function BAR Configuration Register 1 @0x284
    • Virtual Function BAR Configuration Register 0 @0x288
    • Virtual Function BAR Configuration Register 1 @0x28c
    • Virtual Function BAR Configuration Register 0 @0x290
    • Virtual Function BAR Configuration Register 1 @0x294
    • Virtual Function BAR Configuration Register 0 @0x298
    • Virtual Function BAR Configuration Register 1 @0x29c
    • Physical Function Configuration Register @0x2c0
    • Root Complex BAR Configuration Register @0x300
    • Gen 3 Default TX Preset and Rx Preset Hint Register @0x360
    • Gen 3 Gen4 Link Equalization 2ms Timeout Tuning Register @0x364
    • PIPE FIFO Latency Control Register @0x368
    • Gen 4 Default TX Preset Register @0x374
    • PHY register 3, used in GEN4 @0x378
    • Gen 3 Gen 4 Link Equalization Control Register @0x37c
    • Gen 3 Link Equalization Debug Register @0x380
    • Gen 3 Link Equalization Debug Register @0x384
    • Gen 3 Link Equalization Debug Register @0x388
    • Gen 3 Link Equalization Debug Register 0x38c
    • Gen 4 Link Equalization Debug Register @0x3c0
    • Gen 4 Link Equalization Debug Register @0x3c4
    • Gen 4 Link Equalization Debug Register @0x3c8
    • Gen 4 Link Equalization Debug Register @0x3cc
    • ECC Correctable Error Count Register for AXI RAMs @0xc80
    • Low Power Debug and Control Register 0 @0xc88
    • Low Power Debug and Control Register 1 @0xc8c
    • Low Power Debug and Control Register 2 @0xc90
    • Transaction Layer Internal Control Register @0xc94
    • Scaled Flow Control management Register @0xcc4
    • Lane Margining at Receiver Parameters 1 Register @0xcd0
    • Lane Margining at Receiver Parameters 2 Register @0xcd4
    • Lane Margining at Receiver Local Control Register @0xcd8
    • Lane Margining at Receiver Error Status 1 Register @0xcdc
    • Lane Margining at Receiver Error Status 2 Register @0xce0
    • Local Error and Status 2 Register @0xd00
    • Local Interrupt Mask 2 Register @0xd04
    • MSI Mask Cleared Status 1 Register @0xd10
    • MSI Mask Set Status 1 Register @0xd14
    • MSIX Function Mask Cleared Status 1 Register @0xd18
    • MSIX Function Mask Set Status 1 Register @0xd1c
    • MSI Mask Cleared Status 2 Register @0xd20
    • MSI Mask Set Status 2 Register @0xd24
    • MSIX Function Mask Cleared Status 2 Register @0xd28
    • MSIX Function Mask Set Status 2 Register @0xd2c
    • MSI Mask Cleared Status 3 Register @0xd30
    • MSI Mask Set Status 3 Register @0xd34
    • MSIX Function Mask Cleared Status 3 Register @0xd38
    • MSIX Function Mask Set Status 3 Register @0xd3c
    • Link Down Indication Control Register @0xda0
    • PIPE RX Electrical Idle Glitch Control Register @0xda4
    • Equalization Debug Monitor Control Register @0xe4c
    • Equalization Debug Monitor Status 0 Register @0xe50
    • Equalization Debug Monitor Status Register @0xe54
    • AXI Feature Control Register @0xe5c
    • Link Equalization Control 2 Register @0xe60
    • Core Feature Control Register @0xe64
    • Polarity inversion Register @0xe88
    • LTSSM Transition Debug Control Register01 @0xf90
    • LTSSM Transition Debug Control Register23 @0xf94
    • LTSSM Transition Debug Control Register45 @0xf98
    • LTSSM Transition Debug Control Register67 @0xf9c
    • LTSSM Transition Debug Status Register @0xfa0
    • LTSSM Transition Cause Status Register @0xfa4
    • LTSSM Timer Control Register0 @0xfac
    • LTSSM Timer Control Register1 @0xfb0
    • LTSSM Timer Control Register2 @0xfb4
    • LTSSM Timer Control Register3 @0xfb8
  • AXI Configuration Registers
    • Region 0 Outbound AXI to PCIe Address Translation Register 0 @0x0
    • Region 0 Outbound AXI to PCIe Address Translation Register 1 @0x4
    • Region 0 Outbound PCIe Descriptor Register 0 @0x8
    • Region 0 Outbound PCIe Descriptor Register 1 @0xc
    • Region 0 Outbound PCIe Descriptor Register 2 @0x10
    • Region 0 Outbound PCIe Descriptor Register 3 @0x14
    • Region 0 AXI Region Base Address Register 0 @0x18
    • Region 0 AXI Region Base Address 1 @0x1c
    • Region 1 Outbound AXI to PCIe Address Translation Register 0 @0x20
    • Region 1 Outbound AXI to PCIe Address Translation Register 1 @0x24
    • Region 1 Outbound PCIe Descriptor Register 0 @0x28
    • Region 1 Outbound PCIe Descriptor Register 1 @0x2c
    • Region 1 Outbound PCIe Descriptor Register 2 @0x30
    • Region 1 Outbound PCIe Descriptor Register 3 @0x34
    • Region 1 AXI Region Base Address Register 0 @0x38
    • Region 1 AXI Region Base Address 1 @0x3c
    • Region 2 Outbound AXI to PCIe Address Translation Register 0 @0x40
    • Region 2 Outbound AXI to PCIe Address Translation Register 1 @0x44
    • Region 2 Outbound PCIe Descriptor Register 0 @0x48
    • Region 2 Outbound PCIe Descriptor Register 1 @0x4c
    • Region 2 Outbound PCIe Descriptor Register 2 @0x50
    • Region 2 Outbound PCIe Descriptor Register 3 @0x54
    • Region 2 AXI Region Base Address Register 0 @0x58
    • Region 2 AXI Region Base Address 1 @0x5c
    • Region 3 Outbound AXI to PCIe Address Translation Register 0 @0x60
    • Region 3 Outbound AXI to PCIe Address Translation Register 1 @0x64
    • Region 3 Outbound PCIe Descriptor Register 0 @0x68
    • Region 3 Outbound PCIe Descriptor Register 1 @0x6c
    • Region 3 Outbound PCIe Descriptor Register 2 @0x70
    • Region 3 Outbound PCIe Descriptor Register 3 @0x74
    • Region 3 AXI Region Base Address Register 0 @0x78
    • Region 3 AXI Region Base Address 1 @0x7c
    • Region 4 Outbound AXI to PCIe Address Translation Register 0 @0x80
    • Region 4 Outbound AXI to PCIe Address Translation Register 1 @0x84
    • Region 4 Outbound PCIe Descriptor Register 0 @0x88
    • Region 4 Outbound PCIe Descriptor Register 1 @0x8c
    • Region 4 Outbound PCIe Descriptor Register 2 @0x90
    • Region 4 Outbound PCIe Descriptor Register 3 @0x94
    • Region 4 AXI Region Base Address Register 0 @0x98
    • Region 4 AXI Region Base Address 1 @0x9c
    • Region 5 Outbound AXI to PCIe Address Translation Register 0 @0xa0
    • Region 5 Outbound AXI to PCIe Address Translation Register 1 @0xa4
    • Region 5 Outbound PCIe Descriptor Register 0 @0xa8
    • Region 5 Outbound PCIe Descriptor Register 1 @0xac
    • Region 5 Outbound PCIe Descriptor Register 2 @0xb0
    • Region 5 Outbound PCIe Descriptor Register 3 @0xb4
    • Region 5 AXI Region Base Address Register 0 @0xb8
    • Region 5 AXI Region Base Address 1 @0xbc
    • Region 6 Outbound AXI to PCIe Address Translation Register 0 @0xc0
    • Region 6 Outbound AXI to PCIe Address Translation Register 1 @0xc4
    • Region 6 Outbound PCIe Descriptor Register 0 @0xc8
    • Region 6 Outbound PCIe Descriptor Register 1 @0xcc
    • Region 6 Outbound PCIe Descriptor Register 2 @0xd0
    • Region 6 Outbound PCIe Descriptor Register 3 @0xd4
    • Region 6 AXI Region Base Address Register 0 @0xd8
    • Region 6 AXI Region Base Address 1 @0xdc
    • Region 7 Outbound AXI to PCIe Address Translation Register 0 @0xe0
    • Region 7 Outbound AXI to PCIe Address Translation Register 1 @0xe4
    • Region 7 Outbound PCIe Descriptor Register 0 @0xe8
    • Region 7 Outbound PCIe Descriptor Register 1 @0xec
    • Region 7 Outbound PCIe Descriptor Register 2 @0xf0
    • Region 7 Outbound PCIe Descriptor Register 3 @0xf4
    • Region 7 AXI Region Base Address Register 0 @0xf8
    • Region 7 AXI Region Base Address 1 @0xfc
    • Region 8 Outbound AXI to PCIe Address Translation Register 0 @0x100
    • Region 8 Outbound AXI to PCIe Address Translation Register 1 @0x104
    • Region 8 Outbound PCIe Descriptor Register 0 @0x108
    • Region 8 Outbound PCIe Descriptor Register 1 @0x10c
    • Region 8 Outbound PCIe Descriptor Register 2 @0x110
    • Region 8 Outbound PCIe Descriptor Register 3 @0x114
    • Region 8 AXI Region Base Address Register 0 Register 0 Address @0x118
    • Region 8 AXI Region Base Address 1 @0x11c
    • Region 9 Outbound AXI to PCIe Address Translation Register 0 @0x120
    • Region 9 Outbound AXI to PCIe Address Translation Register 1 @0x124
    • Region 9 Outbound PCIe Descriptor Register 0 @0x128
    • Region 9 Outbound PCIe Descriptor Register 1 @0x12c
    • Region 9 Outbound PCIe Descriptor Register 2 @0x130
    • Region 9 Outbound PCIe Descriptor Register 3 @0x134
    • Region 9 AXI Region Base Address Register 0 Register 0 Address @0x138
    • Region 9 AXI Region Base Address 1 @0x13c
    • Region 10 Outbound AXI to PCIe Address Translation Register 0 @0x140
    • Region 10 Outbound AXI to PCIe Address Translation Register 1 @0x144
    • Region 10 Outbound PCIe Descriptor Register 0 @0x148
    • Region 10 Outbound PCIe Descriptor Register 1 @0x14c
    • Region 10 Outbound PCIe Descriptor Register 2 @0x150
    • Region 10 Outbound PCIe Descriptor Register 3 @0x154
    • Region 10 AXI Region Base Address Register 0 Register 0 Address @0x158
    • Region 10 AXI Region Base Address 1 @0x15c
    • Region 11 Outbound AXI to PCIe Address Translation Register 0 @0x160
    • Region 11 Outbound AXI to PCIe Address Translation Register 1 @0x164
    • Region 11 Outbound PCIe Descriptor Register 0 @0x168
    • Region 11 Outbound PCIe Descriptor Register 1 @0x16c
    • Region 11 Outbound PCIe Descriptor Register 2 @0x170
    • Region 11 Outbound PCIe Descriptor Register 3 @0x174
    • Region 11 AXI Region Base Address Register 0 @0x178
    • Region 11 AXI Region Base Address 1 @0x17c
    • Region 12 Outbound AXI to PCIe Address Translation Register 0 @0x180
    • Region 12 Outbound AXI to PCIe Address Translation Register 1 @0x184
    • Region 12 Outbound PCIe Descriptor Register 0 @0x188
    • Region 12 Outbound PCIe Descriptor Register 1 @0x18c
    • Region 12 Outbound PCIe Descriptor Register 2 @0x190
    • Region 12 Outbound PCIe Descriptor Register 3 @0x194
    • Region 12 AXI Region Base Address Register 0 @0x198
    • Region 12 AXI Region Base Address 1 @0x19c
    • Region 13 Outbound AXI to PCIe Address Translation Register 0 @0x1a0
    • Region 13 Outbound AXI to PCIe Address Translation Register 1 @0x1a4
    • Region 13 Outbound PCIe Descriptor Register 0 @0x1a8
    • Region 13 Outbound PCIe Descriptor Register 1 @0x1ac
    • Region 13 Outbound PCIe Descriptor Register 2 @0x1b0
    • Region 13 Outbound PCIe Descriptor Register 3 @0x1b4
    • Region 13 AXI Region Base Address Register 0 @0x1b8
    • Region 13 AXI Region Base Address 1 @0x1bc
    • Region 14 Outbound AXI to PCIe Address Translation Register 0 @0x1c0
    • Region 14 Outbound AXI to PCIe Address Translation Register 1 @0x1c4
    • Region 14 Outbound PCIe Descriptor Register 0 @0x1c8
    • Region 14 Outbound PCIe Descriptor Register 1 @0x1cc
    • Region 14 Outbound PCIe Descriptor Register 2 @0x1d0
    • Region 14 Outbound PCIe Descriptor Register 3 @0x1d4
    • Region 14 AXI Region Base Address Register 0 @0x1d8
    • Region 14 AXI Region Base Address 1 @0x1dc
    • Region 15 Outbound AXI to PCIe Address Translation Register 0 @0x1e0
    • Region 15 Outbound AXI to PCIe Address Translation Register 1 @0x1e4
    • Region 15 Outbound PCIe Descriptor Register 0 @0x1e8
    • Region 15 Outbound PCIe Descriptor Register 1 @0x1ec
    • Region 15 Outbound PCIe Descriptor Register 2 @0x1f0
    • Region 15 Outbound PCIe Descriptor Register 3 @0x1f4
    • Region 15 AXI Region Base Address Register 0 @0x1f8
    • Region 15 AXI Region Base Address 1 @0x1fc
    • Region 16 Outbound AXI to PCIe Address Translation Register 0 @0x200
    • Region 16 Outbound AXI to PCIe Address Translation Register 1 @0x204
    • Region 16 Outbound PCIe Descriptor Register 0 @0x208
    • Region 16 Outbound PCIe Descriptor Register 1 @0x20c
    • Region 16 Outbound PCIe Descriptor Register 2 @0x210
    • Region 16 Outbound PCIe Descriptor Register 3 @0x214
    • Region 16 AXI Region Base Address Register 0 @0x218
    • Region 16 AXI Region Base Address 1 @0x21c
    • Region 17 Outbound AXI to PCIe Address Translation Register 0 @0x220
    • Region 17 Outbound AXI to PCIe Address Translation Register 1 @0x224
    • Region 17 Outbound PCIe Descriptor Register 0 @0x228
    • Region 17 Outbound PCIe Descriptor Register 1 @0x22c
    • Region 17 Outbound PCIe Descriptor Register 2 @0x230
    • Region 17 Outbound PCIe Descriptor Register 3 @0x234
    • Region 17 AXI Region Base Address Register 0 @0x238
    • Region 17 AXI Region Base Address 1 @0x23c
    • Region 18 Outbound AXI to PCIe Address Translation Register 0 @0x240
    • Region 18 Outbound AXI to PCIe Address Translation Register 1 @0x244
    • Region 18 Outbound PCIe Descriptor Register 0 @0x248
    • Region 18 Outbound PCIe Descriptor Register 1 @0x24c
    • Region 18 Outbound PCIe Descriptor Register 2 @0x250
    • Region 18 Outbound PCIe Descriptor Register 3 @0x254
    • Region 18 AXI Region Base Address Register 0 @0x258
    • Region 18 AXI Region Base Address 1 @0x25c
    • Region 19 Outbound AXI to PCIe Address Translation Register 0 @0x260
    • Region 19 Outbound AXI to PCIe Address Translation Register 1 @0x264
    • Region 19 Outbound PCIe Descriptor Register 0 @0x268
    • Region 19 Outbound PCIe Descriptor Register 1 @0x26c
    • Region 19 Outbound PCIe Descriptor Register 2 @0x270
    • Region 19 Outbound PCIe Descriptor Register 3 @0x274
    • Region 19 AXI Region Base Address Register 0 @0x278
    • Region 19 AXI Region Base Address 1 @0x27c
    • Region 20 Outbound AXI to PCIe Address Translation Register 0 @0x280
    • Region 20 Outbound AXI to PCIe Address Translation Register 1 @0x284
    • Region 20 Outbound PCIe Descriptor Register 0 @0x288
    • Region 20 Outbound PCIe Descriptor Register 1 @0x28c
    • Region 20 Outbound PCIe Descriptor Register 2 @0x290
    • Region 20 Outbound PCIe Descriptor Register 3 @0x294
    • Region 20 AXI Region Base Address Register 0 @0x298
    • Region 20 AXI Region Base Address 1 @0x29c
    • Region 21 Outbound AXI to PCIe Address Translation Register 0 @0x2a0
    • Region 21 Outbound AXI to PCIe Address Translation Register 1 @0x2a4
    • Region 21 Outbound PCIe Descriptor Register 0 @0x2a8
    • Region 21 Outbound PCIe Descriptor Register 1 @0x2ac
    • Region 21 Outbound PCIe Descriptor Register 2 @0x2b0
    • Region 21 Outbound PCIe Descriptor Register 3 @0x2b4
    • Region 21 AXI Region Base Address Register 0 @0x2b8
    • Region 21 AXI Region Base Address 1 @0x2bc
    • Region 22 Outbound AXI to PCIe Address Translation Register 0 @0x2c0
    • Region 22 Outbound AXI to PCIe Address Translation Register 1 @0x2c4
    • Region 22 Outbound PCIe Descriptor Register 0 @0x2c8
    • Region 22 Outbound PCIe Descriptor Register 1 @0x2cc
    • Region 22 Outbound PCIe Descriptor Register 2 @0x2d0
    • Region 22 Outbound PCIe Descriptor Register 3 @0x2d4
    • Region 22 AXI Region Base Address Register 0 @0x2d8
    • Region 22 AXI Region Base Address 1 @0x2dc
    • Region 23 Outbound AXI to PCIe Address Translation Register 0 @0x2e0
    • Region 23 Outbound AXI to PCIe Address Translation Register 1 @0x2e4
    • Region 23 Outbound PCIe Descriptor Register 0 @0x2e8
    • Region 23 Outbound PCIe Descriptor Register 1 @0x2ec
    • Region 23 Outbound PCIe Descriptor Register 2 @0x2f0
    • Region 23 Outbound PCIe Descriptor Register 3 @0x2f4
    • Region 23 AXI Region Base Address Register 0 @0x2f8
    • Region 23 AXI Region Base Address 1 @0x2fc
    • Region 24 Outbound AXI to PCIe Address Translation Register 0 @0x300
    • Region 24 Outbound AXI to PCIe Address Translation Register 1 @0x304
    • Region 24 Outbound PCIe Descriptor Register 0 @0x308
    • Region 24 Outbound PCIe Descriptor Register 1 @0x30c
    • Region 24 Outbound PCIe Descriptor Register 2 @0x310
    • Region 24 Outbound PCIe Descriptor Register 3 @0x314
    • Region 24 AXI Region Base Address Register 0 @0x318
    • Region 24 AXI Region Base Address 1 @0x31c
    • Region 25 Outbound AXI to PCIe Address Translation Register 0 @0x320
    • Region 25 Outbound AXI to PCIe Address Translation Register 1 @0x324
    • Region 25 Outbound PCIe Descriptor Register 0 @0x328
    • Region 25 Outbound PCIe Descriptor Register 1 @0x32c
    • Region 25 Outbound PCIe Descriptor Register 2 @0x330
    • Region 25 Outbound PCIe Descriptor Register 3 @0x334
    • Region 25 AXI Region Base Address Register 0 @0x338
    • Region 25 AXI Region Base Address 1 @0x33c
    • Region 26 Outbound AXI to PCIe Address Translation Register 0 @0x340
    • Region 26 Outbound AXI to PCIe Address Translation Register 1 @0x344
    • Region 26 Outbound PCIe Descriptor Register 0 @0x348
    • Region 26 Outbound PCIe Descriptor Register 1 @0x34c
    • Region 26 Outbound PCIe Descriptor Register 2 @0x350
    • Region 26 Outbound PCIe Descriptor Register 3 @0x354
    • Region 26 AXI Region Base Address Register 0 @0x358
    • Region 26 AXI Region Base Address 1 @0x35c
    • Region 27 Outbound AXI to PCIe Address Translation Register 0 @0x360
    • Region 27 Outbound AXI to PCIe Address Translation Register 1 @0x364
    • Region 27 Outbound PCIe Descriptor Register 0 @0x368
    • Region 27 Outbound PCIe Descriptor Register 1 @0x36c
    • Region 27 Outbound PCIe Descriptor Register 2 @0x370
    • Region 27 Outbound PCIe Descriptor Register 3 @0x374
    • Region 27 AXI Region Base Address Register 0 @0x378
    • Region 27 AXI Region Base Address 1 @0x37c
    • Region 28 Outbound AXI to PCIe Address Translation Register 0 @0x380
    • Region 28 Outbound AXI to PCIe Address Translation Register 1 @0x384
    • Region 28 Outbound PCIe Descriptor Register 0 @0x388
    • Region 28 Outbound PCIe Descriptor Register 1 @0x38c
    • Region 28 Outbound PCIe Descriptor Register 2 @0x390
    • Region 28 Outbound PCIe Descriptor Register 3 @0x394
    • Region 28 AXI Region Base Address Register 0 @0x398
    • Region 28 AXI Region Base Address 1 @0x39c
    • Region 29 Outbound AXI to PCIe Address Translation Register 0 @0x3a0
    • Region 29 Outbound AXI to PCIe Address Translation Register 1 @0x3a4
    • Region 29 Outbound PCIe Descriptor Register 0 @0x3a8
    • Region 29 Outbound PCIe Descriptor Register 1 @0x3ac
    • Region 29 Outbound PCIe Descriptor Register 2 @0x3b0
    • Region 29 Outbound PCIe Descriptor Register 3 @0x3b4
    • Region 29 AXI Region Base Address Register 0 @0x3b8
    • Region 29 AXI Region Base Address 1 @0x3bc
    • Region 30 Outbound AXI to PCIe Address Translation Register 0 @0x3c0
    • Region 30 Outbound AXI to PCIe Address Translation Register 1 @0x3c4
    • Region 30 Outbound PCIe Descriptor Register 0 @0x3c8
    • Region 30 Outbound PCIe Descriptor Register 1 @0x3cc
    • Region 30 Outbound PCIe Descriptor Register 2 @0x3d0
    • Region 30 Outbound PCIe Descriptor Register 3 @0x3d4
    • Region 30 AXI Region Base Address Register 0 @0x3d8
    • Region 30 AXI Region Base Address 1 @0x3dc
    • Region 31 Outbound AXI to PCIe Address Translation Register 0 @0x3e0
    • Region 31 Outbound AXI to PCIe Address Translation Register 1 @0x3e4
    • Region 31 Outbound PCIe Descriptor Register 0 @0x3e8
    • Region 31 Outbound PCIe Descriptor Register 1 @0x3ec
    • Region 31 Outbound PCIe Descriptor Register 2 @0x3f0
    • Region 31 Outbound PCIe Descriptor Register 3 @0x3f4
    • Region 31 AXI Region Base Address Register 0 @0x3f8
    • Region 31 AXI Region Base Address 1 @0x3fc
    • BAR 0 Root Port Inbound PCIe to AXI Address Translation Register [31:0] @0x800
    • BAR 0 Root Port Inbound PCIe to AXI Address Translation Register [63:32] @0x804
    • BAR 1 Root Port Inbound PCIe to AXI Address Translation Register [31:0] @0x808
    • BAR 1 Root Port Inbound PCIe to AXI Address Translation Register [63:32] @0x80c
    • BAR 7 Root Port Inbound PCIe to AXI Address Translation Register [31:0] @0x810
    • BAR 7 Root Port Inbound PCIe to AXI Address Translation Register [63:32] @0x814
    • Link Down Indication Bit @0x824
    • Function 0 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x840
    • Function 0 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x844
    • Function 0 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x848
    • Function 0 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x84c
    • Function 0 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x850
    • Function 0 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x854
    • Function 0 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x858
    • Function 0 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x85c
    • Function 0 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x860
    • Function 0 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x864
    • Function 0 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x868
    • Function 0 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x86c
    • Function 0 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x870
    • Function 0 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x874
    • Reserved @0x878
    • Reserved @0x87c
    • Function 1 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x880
    • Function 1 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x884
    • Function 1 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x888
    • Function 1 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x88c
    • Function 1 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x890
    • Function 1 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x894
    • Function 1 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x898
    • Function 1 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x89c
    • Function 1 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8a0
    • Function 1 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8a4
    • Function 1 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8a8
    • Function 1 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8ac
    • Function 1 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8b0
    • Function 1 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8b4
    • Reserved @0x8b8
    • Reserved @0x8bc
    • Function 2 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8c0
    • Function 2 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8c4
    • Function 2 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8c8
    • Function 2 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8cc
    • Function 2 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8d0
    • Function 2 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8d4
    • Function 2 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8d8
    • Function 2 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8dc
    • Function 2 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8e0
    • Function 2 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8e4
    • Function 2 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8e8
    • Function 2 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8ec
    • Function 2 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x8f0
    • Function 2 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x8f4
    • Reserved @0x8f8
    • Reserved @0x8fc
    • Function 3 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x900
    • Function 3 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x904
    • Function 3 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x908
    • Function 3 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x90c
    • Function 3 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x910
    • Function 3 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x914
    • Function 3 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x918
    • Function 3 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x91c
    • Function 3 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x920
    • Function 3 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x924
    • Function 3 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x928
    • Function 3 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x92c
    • Function 3 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x930
    • Function 3 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x934
    • Reserved @0x938
    • Reserved @0x93c
    • Function 4 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x940
    • Function 4 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x944
    • Function 4 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x948
    • Function 4 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x94c
    • Function 4 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x950
    • Function 4 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x954
    • Function 4 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x958
    • Function 4 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x95c
    • Function 4 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x960
    • Function 4 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x964
    • Function 4 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x968
    • Function 4 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x96c
    • Function 4 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x970
    • Function 4 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x974
    • Reserved @0x978
    • Reserved @0x97c
    • Function 5 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x980
    • Function 5 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x984
    • Function 5 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x988
    • Function 5 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x98c
    • Function 5 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x990
    • Function 5 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x994
    • Function 5 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x998
    • Function 5 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x99c
    • Function 5 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9a0
    • Function 5 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9a4
    • Function 5 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9a8
    • Function 5 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9ac
    • Function 5 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9b0
    • Function 5 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9b4
    • Reserved @0x9b8
    • Reserved @0x9bc
    • Function 6 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9c0
    • Function 6 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9c4
    • Function 6 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9c8
    • Function 6 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9cc
    • Function 6 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9d0
    • Function 6 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9d4
    • Function 6 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9d8
    • Function 6 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9dc
    • Function 6 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9e0
    • Function 6 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9e4
    • Function 6 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9e8
    • Function 6 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9ec
    • Function 6 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x9f0
    • Function 6 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x9f4
    • Reserved @0x9f8
    • Reserved @0x9fc
    • Function 7 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa00
    • Function 7 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa04
    • Function 7 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa08
    • Function 7 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa0c
    • Function 7 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa10
    • Function 7 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa14
    • Function 7 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa18
    • Function 7 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa1c
    • Function 7 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa20
    • Function 7 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa24
    • Function 7 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa28
    • Function 7 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa2c
    • Function 7 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa30
    • Function 7 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa34
    • Reserved @0xa38
    • Reserved @0xa3c
    • Function 8 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa40
    • Function 8 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa44
    • Function 8 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa48
    • Function 8 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa4c
    • Function 8 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa50
    • Function 8 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa54
    • Function 8 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa58
    • Function 8 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa5c
    • Function 8 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa60
    • Function 8 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa64
    • Function 8 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa68
    • Function 8 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa6c
    • Function 8 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa70
    • Function 8 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa74
    • Reserved @0xa78
    • Reserved @0xa7c
    • Function 9 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa80
    • Function 9 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa84
    • Function 9 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa88
    • Function 9 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa8c
    • Function 9 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa90
    • Function 9 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa94
    • Function 9 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xa98
    • Function 9 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xa9c
    • Function 9 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xaa0
    • Function 9 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xaa4
    • Function 9 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xaa8
    • Function 9 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xaac
    • Function 9 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xab0
    • Function 9 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xab4
    • Reserved @0xab8
    • Reserved @0xabc
    • Function 10 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xac0
    • Function 10 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xac4
    • Function 10 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xac8
    • Function 10 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xacc
    • Function 10 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xad0
    • Function 10 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xad4
    • Function 10 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xad8
    • Function 10 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xadc
    • Function 10 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xae0
    • Function 10 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xae4
    • Function 10 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xae8
    • Function 10 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xaec
    • Function 10 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xaf0
    • Function 10 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xaf4
    • Reserved @0xaf8
    • Reserved @0xafc
    • Function 11 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb00
    • Function 11 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb04
    • Function 11 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb08
    • Function 11 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb0c
    • Function 11 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb10
    • Function 11 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb14
    • Function 11 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb18
    • Function 11 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb1c
    • Function 11 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb20
    • Function 11 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb24
    • Function 11 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb28
    • Function 11 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb2c
    • Function 11 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb30
    • Function 11 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb34
    • Reserved @0xb38
    • Reserved @0xb3c
    • Function 12 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb40
    • Function 12 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb44
    • Function 12 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb48
    • Function 12 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb4c
    • Function 12 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb50
    • Function 12 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb54
    • Function 12 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb58
    • Function 12 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb5c
    • Function 12 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb60
    • Function 12 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb64
    • Function 12 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb68
    • Function 12 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb6c
    • Function 12 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb70
    • Function 12 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb74
    • Reserved @0xb78
    • Reserved @0xb7c
    • Function 13 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb80
    • Function 13 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb84
    • Function 13 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb88
    • Function 13 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb8c
    • Function 13 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb90
    • Function 13 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb94
    • Function 13 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xb98
    • Function 13 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xb9c
    • Function 13 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xba0
    • Function 13 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xba4
    • Function 13 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xba8
    • Function 13 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbac
    • Function 13 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbb0
    • Function 13 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbb4
    • Reserved @0xbb8
    • Reserved @0xbbc
    • Function 14 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbc0
    • Function 14 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbc4
    • Function 14 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbc8
    • Function 14 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbcc
    • Function 14 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbd0
    • Function 14 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbd4
    • Function 14 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbd8
    • Function 14 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbdc
    • Function 14 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbe0
    • Function 14 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbe4
    • Function 14 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbe8
    • Function 14 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbec
    • Function 14 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xbf0
    • Function 14 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xbf4
    • Reserved @0xbf8
    • Reserved @0xbfc
    • Function 15 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc00
    • Function 15 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc04
    • Function 15 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc08
    • Function 15 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc0c
    • Function 15 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc10
    • Function 15 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc14
    • Function 15 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc18
    • Function 15 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc1c
    • Function 15 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc20
    • Function 15 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc24
    • Function 15 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc28
    • Function 15 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc2c
    • Function 15 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc30
    • Function 15 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc34
    • Reserved @0xc38
    • Reserved @0xc3c
    • Function 16 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc40
    • Function 16 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc44
    • Function 16 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc48
    • Function 16 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc4c
    • Function 16 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc50
    • Function 16 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc54
    • Function 16 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc58
    • Function 16 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc5c
    • Function 16 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc60
    • Function 16 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc64
    • Function 16 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc68
    • Function 16 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc6c
    • Function 16 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc70
    • Function 16 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc74
    • Reserved @0xc78
    • Reserved @0xc7c
    • Function 17 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc80
    • Function 17 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc84
    • Function 17 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc88
    • Function 17 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc8c
    • Function 17 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc90
    • Function 17 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc94
    • Function 17 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xc98
    • Function 17 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xc9c
    • Function 17 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xca0
    • Function 17 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xca4
    • Function 17 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xca8
    • Function 17 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xcac
    • Function 17 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xcb0
    • Function 17 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xcb4
    • Reserved @0xcb8
    • Reserved @0xcbc
    • Function 18 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xcc0
    • Function 18 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xcc4
    • Function 18 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xcc8
    • Function 18 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xccc
    • Function 18 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xcd0
    • Function 18 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xcd4
    • Function 18 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xcd8
    • Function 18 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xcdc
    • Function 18 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xce0
    • Function 18 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xce4
    • Function 18 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xce8
    • Function 18 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xcec
    • Function 18 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xcf0
    • Function 18 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xcf4
    • Reserved @0xcf8
    • Reserved @0xcfc
    • Function 19 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd00
    • Function 19 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd04
    • Function 19 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd08
    • Function 19 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd0c
    • Function 19 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd10
    • Function 19 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd14
    • Function 19 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd18
    • Function 19 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd1c
    • Function 19 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd20
    • Function 19 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd24
    • Function 19 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd28
    • Function 19 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd2c
    • Function 19 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd30
    • Function 19 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd34
    • Reserved @0xd38
    • Reserved @0xd3c
    • Function 20 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd40
    • Function 20 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd44
    • Function 20 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd48
    • Function 20 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd4c
    • Function 20 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd50
    • Function 20 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd54
    • Function 20 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd58
    • Function 20 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd5c
    • Function 20 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd60
    • Function 20 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd64
    • Function 20 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd68
    • Function 20 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd6c
    • Function 20 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd70
    • Function 20 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd74
    • Reserved @0xd78
    • Reserved @0xd7c
    • Function 21 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd80
    • Function 21 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd84
    • Function 21 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd88
    • Function 21 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd8c
    • Function 21 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd90
    • Function 21 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd94
    • Function 21 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xd98
    • Function 21 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xd9c
    • Function 21 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xda0
    • Function 21 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xda4
    • Function 21 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xda8
    • Function 21 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xdac
    • Function 21 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xdb0
    • Function 21 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xdb4
    • Reserved @0xdb8
    • Reserved @0xdbc
    • Function 22 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xdc0
    • Function 22 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xdc4
    • Function 22 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xdc8
    • Function 22 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xdcc
    • Function 22 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xdd0
    • Function 22 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xdd4
    • Function 22 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xdd8
    • Function 22 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xddc
    • Function 22 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xde0
    • Function 22 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xde4
    • Function 22 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xde8
    • Function 22 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xdec
    • Function 22 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xdf0
    • Function 22 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xdf4
    • Reserved @0xdf8
    • Reserved @0xdfc
    • Function 23 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe00
    • Function 23 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe04
    • Function 23 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe08
    • Function 23 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe0c
    • Function 23 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe10
    • Function 23 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe14
    • Function 23 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe18
    • Function 23 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe1c
    • Function 23 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe20
    • Function 23 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe24
    • Function 23 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe28
    • Function 23 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe2c
    • Function 23 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe30
    • Function 23 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe34
    • Reserved @0xe38
    • Reserved @0xe3c
    • Function 24 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe40
    • Function 24 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe44
    • Function 24 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe48
    • Function 24 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe4c
    • Function 24 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe50
    • Function 24 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe54
    • Function 24 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe58
    • Function 24 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe5c
    • Function 24 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe60
    • Function 24 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe64
    • Function 24 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe68
    • Function 24 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe6c
    • Function 24 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe70
    • Function 24 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe74
    • Reserved @0xe78
    • Reserved @0xe7c
    • Function 25 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe80
    • Function 25 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe84
    • Function 25 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe88
    • Function 25 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe8c
    • Function 25 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe90
    • Function 25 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe94
    • Function 25 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xe98
    • Function 25 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xe9c
    • Function 25 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xea0
    • Function 25 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xea4
    • Function 25 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xea8
    • Function 25 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xeac
    • Function 25 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xeb0
    • Function 25 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xeb4
    • Reserved @0xeb8
    • Reserved @0xebc
    • Function 26 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xec0
    • Function 26 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xec4
    • Function 26 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xec8
    • Function 26 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xecc
    • Function 26 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xed0
    • Function 26 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xed4
    • Function 26 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xed8
    • Function 26 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xedc
    • Function 26 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xee0
    • Function 26 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xee4
    • Function 26 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xee8
    • Function 26 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xeec
    • Function 26 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xef0
    • Function 26 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xef4
    • Reserved @0xef8
    • Reserved @0xefc
    • Function 27 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf00
    • Function 27 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf04
    • Function 27 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf08
    • Function 27 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf0c
    • Function 27 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf10
    • Function 27 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf14
    • Function 27 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf18
    • Function 27 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf1c
    • Function 27 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf20
    • Function 27 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf24
    • Function 27 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf28
    • Function 27 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf2c
    • Function 27 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf30
    • Function 27 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf34
    • Reserved @0xf38
    • Reserved @0xf3c
    • Function 28 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf40
    • Function 28 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf44
    • Function 28 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf48
    • Function 28 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf4c
    • Function 28 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf50
    • Function 28 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf54
    • Function 28 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf58
    • Function 28 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf5c
    • Function 28 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf60
    • Function 28 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf64
    • Function 28 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf68
    • Function 28 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf6c
    • Function 28 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf70
    • Function 28 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf74
    • Reserved @0xf78
    • Reserved @0xf7c
    • Function 29 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf80
    • Function 29 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf84
    • Function 29 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf88
    • Function 29 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf8c
    • Function 29 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf90
    • Function 29 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf94
    • Function 29 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xf98
    • Function 29 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xf9c
    • Function 29 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfa0
    • Function 29 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfa4
    • Function 29 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfa8
    • Function 29 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfac
    • Function 29 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfb0
    • Function 29 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfb4
    • Reserved @0xfb8
    • Reserved @0xfbc
    • Function 30 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfc0
    • Function 30 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfc4
    • Function 30 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfc8
    • Function 30 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfcc
    • Function 30 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfd0
    • Function 30 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfd4
    • Function 30 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfd8
    • Function 30 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfdc
    • Function 30 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfe0
    • Function 30 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfe4
    • Function 30 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xfe8
    • Function 30 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xfec
    • Function 30 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0xff0
    • Function 30 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0xff4
    • Reserved @0xff8
    • Reserved @0xffc
    • Function 31 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1000
    • Function 31 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1004
    • Function 31 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1008
    • Function 31 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x100c
    • Function 31 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1010
    • Function 31 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1014
    • Function 31 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1018
    • Function 31 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x101c
    • Function 31 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1020
    • Function 31 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1024
    • Function 31 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1028
    • Function 31 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x102c
    • Function 31 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1030
    • Function 31 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1034
    • Reserved @0x1038
    • Reserved @0x103c
    • Function 32 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1040
    • Function 32 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1044
    • Function 32 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1048
    • Function 32 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x104c
    • Function 32 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1050
    • Function 32 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1054
    • Function 32 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1058
    • Function 32 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x105c
    • Function 32 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1060
    • Function 32 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1064
    • Function 32 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1068
    • Function 32 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x106c
    • Function 32 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1070
    • Function 32 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1074
    • Reserved @0x1078
    • Reserved @0x107c
    • Function 33 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1080
    • Function 33 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1084
    • Function 33 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1088
    • Function 33 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x108c
    • Function 33 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1090
    • Function 33 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1094
    • Function 33 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1098
    • Function 33 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x109c
    • Function 33 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10a0
    • Function 33 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10a4
    • Function 33 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10a8
    • Function 33 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10ac
    • Function 33 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10b0
    • Function 33 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10b4
    • Reserved @0x10b8
    • Reserved @0x10bc
    • Function 34 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10c0
    • Function 34 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10c4
    • Function 34 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10c8
    • Function 34 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10cc
    • Function 34 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10d0
    • Function 34 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10d4
    • Function 34 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10d8
    • Function 34 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10dc
    • Function 34 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10e0
    • Function 34 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10e4
    • Function 34 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10e8
    • Function 34 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10ec
    • Function 34 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x10f0
    • Function 34 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x10f4
    • Reserved @0x10f8
    • Reserved @0x10fc
    • Function 35 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1100
    • Function 35 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1104
    • Function 35 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1108
    • Function 35 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x110c
    • Function 35 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1110
    • Function 35 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1114
    • Function 35 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1118
    • Function 35 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x111c
    • Function 35 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1120
    • Function 35 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1124
    • Function 35 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1128
    • Function 35 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x112c
    • Function 35 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1130
    • Function 35 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1134
    • Reserved @0x1138
    • Reserved @0x113c
    • Function 36 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1140
    • Function 36 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1144
    • Function 36 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1148
    • Function 36 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x114c
    • Function 36 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1150
    • Function 36 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1154
    • Function 36 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1158
    • Function 36 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x115c
    • Function 36 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1160
    • Function 36 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1164
    • Function 36 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1168
    • Function 36 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x116c
    • Function 36 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1170
    • Function 36 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1174
    • Reserved @0x1178
    • Reserved @0x117c
    • Function 37 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1180
    • Function 37 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1184
    • Function 37 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1188
    • Function 37 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x118c
    • Function 37 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1190
    • Function 37 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1194
    • Function 37 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1198
    • Function 37 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x119c
    • Function 37 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11a0
    • Function 37 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11a4
    • Function 37 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11a8
    • Function 37 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11ac
    • Function 37 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11b0
    • Function 37 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11b4
    • Reserved @0x11b8
    • Reserved @0x11bc
    • Function 38 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11c0
    • Function 38 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11c4
    • Function 38 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11c8
    • Function 38 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11cc
    • Function 38 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11d0
    • Function 38 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11d4
    • Function 38 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11d8
    • Function 38 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11dc
    • Function 38 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11e0
    • Function 38 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11e4
    • Function 38 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11e8
    • Function 38 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11ec
    • Function 38 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x11f0
    • Function 38 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x11f4
    • Reserved @0x11f8
    • Reserved @0x11fc
    • Function 39 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1200
    • Function 39 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1204
    • Function 39 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1208
    • Function 39 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x120c
    • Function 39 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1210
    • Function 39 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1214
    • Function 39 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1218
    • Function 39 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x121c
    • Function 39 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1220
    • Function 39 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1224
    • Function 39 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1228
    • Function 39 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x122c
    • Function 39 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1230
    • Function 39 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1234
    • Reserved @0x1238
    • Reserved @0x123c
    • Function 40 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1240
    • Function 40 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1244
    • Function 40 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1248
    • Function 40 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x124c
    • Function 40 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1250
    • Function 40 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1254
    • Function 40 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1258
    • Function 40 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x125c
    • Function 40 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1260
    • Function 40 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1264
    • Function 40 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1268
    • Function 40 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x126c
    • Function 40 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1270
    • Function 40 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1274
    • Reserved @0x1278
    • Reserved @0x127c
    • Function 41 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1280
    • Function 41 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1284
    • Function 41 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1288
    • Function 41 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x128c
    • Function 41 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1290
    • Function 41 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1294
    • Function 41 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1298
    • Function 41 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x129c
    • Function 41 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12a0
    • Function 41 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12a4
    • Function 41 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12a8
    • Function 41 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12ac
    • Function 41 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12b0
    • Function 41 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12b4
    • Reserved @0x12b8
    • Reserved @0x12bc
    • Function 42 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12c0
    • Function 42 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12c4
    • Function 42 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12c8
    • Function 42 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12cc
    • Function 42 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12d0
    • Function 42 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12d4
    • Function 42 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12d8
    • Function 42 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12dc
    • Function 42 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12e0
    • Function 42 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12e4
    • Function 42 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12e8
    • Function 42 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12ec
    • Function 42 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x12f0
    • Function 42 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x12f4
    • Reserved @0x12f8
    • Reserved @0x12fc
    • Function 43 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1300
    • Function 43 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1304
    • Function 43 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1308
    • Function 43 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x130c
    • Function 43 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1310
    • Function 43 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1314
    • Function 43 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1318
    • Function 43 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x131c
    • Function 43 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1320
    • Function 43 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1324
    • Function 43 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1328
    • Function 43 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x132c
    • Function 43 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1330
    • Function 43 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1334
    • Reserved @0x1338
    • Reserved @0x133c
    • Function 44 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1340
    • Function 44 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1344
    • Function 44 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1348
    • Function 44 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x134c
    • Function 44 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1350
    • Function 44 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1354
    • Function 44 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1358
    • Function 44 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x135c
    • Function 44 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1360
    • Function 44 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1364
    • Function 44 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1368
    • Function 44 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x136c
    • Function 44 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1370
    • Function 44 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1374
    • Reserved @0x1378
    • Reserved @0x137c
    • Function 45 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1380
    • Function 45 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1384
    • Function 45 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1388
    • Function 45 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x138c
    • Function 45 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1390
    • Function 45 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1394
    • Function 45 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1398
    • Function 45 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x139c
    • Function 45 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13a0
    • Function 45 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13a4
    • Function 45 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13a8
    • Function 45 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13ac
    • Function 45 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13b0
    • Function 45 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13b4
    • Reserved @0x13b8
    • Reserved @0x13bc
    • Function 46 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13c0
    • Function 46 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13c4
    • Function 46 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13c8
    • Function 46 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13cc
    • Function 46 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13d0
    • Function 46 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13d4
    • Function 46 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13d8
    • Function 46 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13dc
    • Function 46 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13e0
    • Function 46 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13e4
    • Function 46 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13e8
    • Function 46 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13ec
    • Function 46 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x13f0
    • Function 46 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x13f4
    • Reserved @0x13f8
    • Reserved @0x13fc
    • Function 47 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1400
    • Function 47 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1404
    • Function 47 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1408
    • Function 47 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x140c
    • Function 47 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1410
    • Function 47 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1414
    • Function 47 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1418
    • Function 47 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x141c
    • Function 47 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1420
    • Function 47 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1424
    • Function 47 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1428
    • Function 47 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x142c
    • Function 47 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1430
    • Function 47 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1434
    • Reserved @0x1438
    • Reserved @0x143c
    • Function 48 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1440
    • Function 48 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1444
    • Function 48 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1448
    • Function 48 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x144c
    • Function 48 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1450
    • Function 48 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1454
    • Function 48 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1458
    • Function 48 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x145c
    • Function 48 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1460
    • Function 48 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1464
    • Function 48 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1468
    • Function 48 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x146c
    • Function 48 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1470
    • Function 48 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1474
    • Reserved @0x1478
    • Reserved @0x147c
    • Function 49 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1480
    • Function 49 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1484
    • Function 49 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1488
    • Function 49 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x148c
    • Function 49 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1490
    • Function 49 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1494
    • Function 49 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1498
    • Function 49 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x149c
    • Function 49 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14a0
    • Function 49 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14a4
    • Function 49 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14a8
    • Function 49 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14ac
    • Function 49 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14b0
    • Function 49 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14b4
    • Reserved @0x14b8
    • Reserved @0x14bc
    • Function 50 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14c0
    • Function 50 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14c4
    • Function 50 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14c8
    • Function 50 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14cc
    • Function 50 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14d0
    • Function 50 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14d4
    • Function 50 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14d8
    • Function 50 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14dc
    • Function 50 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14e0
    • Function 50 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14e4
    • Function 50 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14e8
    • Function 50 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14ec
    • Function 50 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x14f0
    • Function 50 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x14f4
    • Reserved @0x14f8
    • Reserved @0x14fc
    • Function 51 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1500
    • Function 51 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1504
    • Function 51 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1508
    • Function 51 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x150c
    • Function 51 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1510
    • Function 51 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1514
    • Function 51 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1518
    • Function 51 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x151c
    • Function 51 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1520
    • Function 51 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1524
    • Function 51 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1528
    • Function 51 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x152c
    • Function 51 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1530
    • Function 51 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1534
    • Reserved @0x1538
    • Reserved @0x153c
    • Function 52 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1540
    • Function 52 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1544
    • Function 52 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1548
    • Function 52 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x154c
    • Function 52 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1550
    • Function 52 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1554
    • Function 52 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1558
    • Function 52 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x155c
    • Function 52 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1560
    • Function 52 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1564
    • Function 52 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1568
    • Function 52 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x156c
    • Function 52 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1570
    • Function 52 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1574
    • Reserved @0x1578
    • Reserved @0x157c
    • Function 53 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1580
    • Function 53 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1584
    • Function 53 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1588
    • Function 53 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x158c
    • Function 53 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1590
    • Function 53 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1594
    • Function 53 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1598
    • Function 53 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x159c
    • Function 53 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15a0
    • Function 53 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15a4
    • Function 53 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15a8
    • Function 53 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15ac
    • Function 53 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15b0
    • Function 53 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15b4
    • Reserved @0x15b8
    • Reserved @0x15bc
    • Function 54 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15c0
    • Function 54 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15c4
    • Function 54 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15c8
    • Function 54 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15cc
    • Function 54 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15d0
    • Function 54 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15d4
    • Function 54 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15d8
    • Function 54 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15dc
    • Function 54 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15e0
    • Function 54 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15e4
    • Function 54 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15e8
    • Function 54 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15ec
    • Function 54 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x15f0
    • Function 54 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x15f4
    • Reserved @0x15f8
    • Reserved @0x15fc
    • Function 55 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1600
    • Function 55 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1604
    • Function 55 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1608
    • Function 55 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x160c
    • Function 55 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1610
    • Function 55 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1614
    • Function 55 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1618
    • Function 55 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x161c
    • Function 55 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1620
    • Function 55 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1624
    • Function 55 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1628
    • Function 55 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x162c
    • Function 55 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1630
    • Function 55 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1634
    • Reserved @0x1638
    • Reserved @0x163c
    • Function 56 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1640
    • Function 56 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1644
    • Function 56 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1648
    • Function 56 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x164c
    • Function 56 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1650
    • Function 56 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1654
    • Function 56 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1658
    • Function 56 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x165c
    • Function 56 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1660
    • Function 56 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1664
    • Function 56 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1668
    • Function 56 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x166c
    • Function 56 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1670
    • Function 56 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1674
    • Reserved @0x1678
    • Reserved @0x167c
    • Function 57 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1680
    • Function 57 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1684
    • Function 57 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1688
    • Function 57 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x168c
    • Function 57 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1690
    • Function 57 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1694
    • Function 57 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1698
    • Function 57 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x169c
    • Function 57 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16a0
    • Function 57 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16a4
    • Function 57 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16a8
    • Function 57 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16ac
    • Function 57 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16b0
    • Function 57 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16b4
    • Reserved @0x16b8
    • Reserved @0x16bc
    • Function 58 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16c0
    • Function 58 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16c4
    • Function 58 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16c8
    • Function 58 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16cc
    • Function 58 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16d0
    • Function 58 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16d4
    • Function 58 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16d8
    • Function 58 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16dc
    • Function 58 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16e0
    • Function 58 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16e4
    • Function 58 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16e8
    • Function 58 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16ec
    • Function 58 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x16f0
    • Function 58 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x16f4
    • Reserved @0x16f8
    • Reserved @0x16fc
    • Function 59 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1700
    • Function 59 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1704
    • Function 59 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1708
    • Function 59 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x170c
    • Function 59 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1710
    • Function 59 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1714
    • Function 59 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1718
    • Function 59 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x171c
    • Function 59 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1720
    • Function 59 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1724
    • Function 59 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1728
    • Function 59 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x172c
    • Function 59 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1730
    • Function 59 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1734
    • Reserved @0x1738
    • Reserved @0x173c
    • Function 60 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1740
    • Function 60 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1744
    • Function 60 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1748
    • Function 60 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x174c
    • Function 60 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1750
    • Function 60 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1754
    • Function 60 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1758
    • Function 60 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x175c
    • Function 60 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1760
    • Function 60 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1764
    • Function 60 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1768
    • Function 60 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x176c
    • Function 60 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1770
    • Function 60 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1774
    • Reserved @0x1778
    • Reserved @0x177c
    • Function 61 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1780
    • Function 61 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1784
    • Function 61 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1788
    • Function 61 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x178c
    • Function 61 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1790
    • Function 61 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1794
    • Function 61 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1798
    • Function 61 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x179c
    • Function 61 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17a0
    • Function 61 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17a4
    • Function 61 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17a8
    • Function 61 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17ac
    • Function 61 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17b0
    • Function 61 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17b4
    • Reserved @0x17b8
    • Reserved @0x17bc
    • Function 62 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17c0
    • Function 62 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17c4
    • Function 62 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17c8
    • Function 62 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17cc
    • Function 62 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17d0
    • Function 62 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17d4
    • Function 62 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17d8
    • Function 62 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17dc
    • Function 62 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17e0
    • Function 62 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17e4
    • Function 62 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17e8
    • Function 62 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17ec
    • Function 62 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x17f0
    • Function 62 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x17f4
    • Reserved @0x17f8
    • Reserved @0x17fc
    • Function 63 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1800
    • Function 63 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1804
    • Function 63 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1808
    • Function 63 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x180c
    • Function 63 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1810
    • Function 63 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1814
    • Function 63 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1818
    • Function 63 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x181c
    • Function 63 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1820
    • Function 63 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1824
    • Function 63 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1828
    • Function 63 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x182c
    • Function 63 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1830
    • Function 63 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1834
    • Reserved @0x1838
    • Reserved @0x183c
    • Function 64 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1840
    • Function 64 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1844
    • Function 64 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1848
    • Function 64 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x184c
    • Function 64 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1850
    • Function 64 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1854
    • Function 64 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1858
    • Function 64 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x185c
    • Function 64 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1860
    • Function 64 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1864
    • Function 64 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1868
    • Function 64 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x186c
    • Function 64 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1870
    • Function 64 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1874
    • Reserved @0x1878
    • Reserved @0x187c
    • Function 65 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1880
    • Function 65 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1884
    • Function 65 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1888
    • Function 65 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x188c
    • Function 65 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1890
    • Function 65 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1894
    • Function 65 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1898
    • Function 65 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x189c
    • Function 65 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18a0
    • Function 65 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18a4
    • Function 65 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18a8
    • Function 65 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18ac
    • Function 65 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18b0
    • Function 65 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18b4
    • Reserved @0x18b8
    • Reserved @0x18bc
    • Function 66 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18c0
    • Function 66 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18c4
    • Function 66 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18c8
    • Function 66 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18cc
    • Function 66 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18d0
    • Function 66 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18d4
    • Function 66 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18d8
    • Function 66 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18dc
    • Function 66 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18e0
    • Function 66 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18e4
    • Function 66 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18e8
    • Function 66 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18ec
    • Function 66 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x18f0
    • Function 66 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x18f4
    • Reserved @0x18f8
    • Reserved @0x18fc
    • Function 67 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1900
    • Function 67 BAR 0 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1904
    • Function 67 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1908
    • Function 67 BAR 1 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x190c
    • Function 67 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1910
    • Function 67 BAR 2 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1914
    • Function 67 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1918
    • Function 67 BAR 3 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x191c
    • Function 67 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1920
    • Function 67 BAR 4 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1924
    • Function 67 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1928
    • Function 67 BAR 5 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x192c
    • Function 67 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 0 [31:0] @0x1930
    • Function 67 BAR 6 Endpoint Inbound PCIe to AXI Address Translation Register 1 [63:32] @0x1934
    • Reserved @0x1938
    • Reserved @0x193c
  • Revision History

Revision History

Table 1. Document Revision History
Date Version Description
December 2025 1.1 Added Root Port Configuration Register Set. (DOC-2831)
Updated Debug Mux Control Register @0x208.
July 2024 1.0 Initial release.