VF Base Address Register 0 @0x224
This is part of the set of six Virtual Function Base Address Registers defined by the SR-IOV Specifications. These registers are used to define address ranges for memory accesses to the Endpoint device. This register may be used to define a range of 32-bit addresses, or paired with the next adjacent register to define a 64-bit address range. During the initial configuration of the device, the configuration program determines the size of the address range defined by the BAR by writing a pattern of all 1's into the BAR, reading back from the BAR, and noting the position of the first 1 (the most significant) in the returned value. A value of 0 is returned by the Controller if this BAR is not configured. Otherwise, the number of 1's returned is based on the length of the BAR.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | Memory Space Indicator [MSI] | Specifies whether this BAR defines a memory address range or an I/O address range (0 = memory, 1 = I/O). The value read in this field is determined by the setting of BAR Configuration Registers of the associated Physical Function. | 0x0 |
| 1 | R | Reserved [R7] | This bit is hardwired to 0 for both memory and I/O BARs. | 0x0 |
| 2 | R | Size [S0] | When the BAR is used to define a memory address range, this field indicates whether the address range is 32-bit or 64-bit (0 = 32-bit, 1 = 64 bit). For 64-bit address ranges, the value in BAR 1 is treated as a continuation of the base address in BAR 0. The value read in this field is determined by the setting of BAR Configuration Registers of the associated Physical Function. | 0x1 |
| 3 | R | Prefetchability [P0] | When the BAR is used to define a memory address range, this field declares whether data from the address range is prefetchable (0 = non-prefetchable, 1 = prefetchable). The value read in this field is determined by the setting of BAR Configuration Registers of the associated Physical Function. | 0x0 |
| 7:4 | R | Reserved [R8] | These bits are hardwired to 0 | 0x0 |
| 21:8 | R | Base Address - RO part [BAMR0] | This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated Physical Function. All other bits are not writeable, and are read as 0's. | 0x0 |
| 31:22 | R/W | Base Address - RW part [BAMRW] | This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated Physical Function. | 0x0 |