Lane Equalization Control Register 0 @0x30c
This register contains the 8.0GT/s Transmitter Preset and the Receiver Preset Hint values for lanes 0 and 1, received from the Upstream Device during the Link Equalization procedure.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 6:0 | R | Reserved [R0] | Reserved | 0x00 |
| 7 | R | Reserved [R0_1] | Reserved | 0x0 |
| 11:8 | R | Upstream Port 8.0GT/ s Transmitter Preset [UPTP0] | 8.0GT/s Lane 0 Transmitter Preset value received from the upstream device. | 0xf |
| 14:12 | R | Upstream Port 8.0GT/s Receiver Preset Hint [UPRPH0] | 8.0GT/s Lane 0 Receiver Preset Hint value received from the upstream device. | 0x7 |
| 15 | R | Reserved [R1] | Reserved | 0x0 |
| 22:16 | R | Reserved [R2] | Reserved | 0x00 |
| 23 | R | Reserved [R2_1] | Reserved | 0x0 |
| 27:24 | R | Upstream Port 8.0GT/ s Transmitter Preset [UPTP1] | 8.0GT/s Lane 1 Transmitter Preset value received from the upstream device. | 0xf |
| 30:28 | R | Upstream Port 8.0GT/s Receiver Preset Hint [UPRPH1] | 8.0GT/s Lane 1 Receiver Preset Hint value received from the upstream device. | 0x7 |
| 31 | R | Reserved [R3] | Reserved | 0x0 |