Power Management Control/Status Report @0x84

This location contains the Power Management Control/Status and Data Registers.

Table 1. i_pwr_mgmt_ctrl_stat_rep
Bits	SW	Name	Description	Reset
1:0	R/W	Power State [PS]	Indicates the power state this Function is currently in. This field can be read by the software to monitor the current power state, or can be written to cause a transition to a new state. The valid settings are 00 (state D0), 01 (state D1) and 11 (state D3hot). The software should not write any other value into this field. This field can also be written from the local management bus independently for each Function.	0x0
2	R	Reserved [R4]	Reserved	0x0
3	R	No Soft Reset [NSR]	When this bit is set to 1, the Function will maintain all its state in the PM state D3hot. The software is not required to re-initialize the Function registers on the transition back to D0. This bit is set to 1 by default, but can be modified independently for each PF from the local management bus.	0x01
7:4	R	Reserved [R3]	Reserved	0x0
8	R/W	PME Enable [PE]	Setting this bit enables the notification of PME events from the associated Function. This bit can be set also by writing into this register from the local management bus. This is a sticky field.	0x0
14:9	R	Reserved [R2]	Reserved	0x0
15	R/WOCLR	PME Status [PMES]	When PME notification is enabled, writing a 1 into this bit position from the local management bus sets this bit and causes the Controller to send a PME message from the associated Function. When the Root Complex processes this message, it will turn off this bit by writing a 1 into this bit position through a Config Write. This bit can be set or cleared from the local management bus by writing a 1 or 0, respectively. It can only be cleared from the configuration path (by writing a 1). This is a sticky field.	0x0
23:16	R	Reserved [R1]	Reserved	0x0
31:24	R	Data Register [DR]	This optional register is not implemented in the PCIe Controller. This field is hardwired to 0.	0x0