Link Control and Status Register 2 @0xf0

This register contains control and status bits specific to the PCI Express link. All the fields marked RW or RW(STICKY) can also be written from the local management bus.

Table 1. i_link_ctrl_status_2
Bits SW Name Description Reset
3:0 R/W Target Link Speed [TLS] For an upstream component, this field sets an upper limit on Link operational speed during reconfiguration. Additionally for both upstream and downstream components, this field sets the target speed when the software forces the link into Compliance mode by setting the Enter Compliance bit in this register (0001 = 2.5 GT/s, 0010 = 5 GT/s, 0011 = 8 GT/s, 0100 = 16 GT/s). The default value of this field is 0001 (2.5 GT/s) when the PCIE_GENERATION_SEL strap pins of the Controller are set to 000, 0010 (5 GT/s) when the strap is set to 001, 0011 (8 GT/s) when the strap pin is set to 010, and 0100 (16 GT/s) when the strap pin is set to 011. These bits are STICKY. 4'd4
4 R/W Enter Compliance [EC] This bit is used to force the Endpoint device to enter Compliance mode. Software sets this bit to 1 and initiates a hot reset to force the device into Compliance mode. The target speed for Compliance mode is determined by the Target Link Speed field of this register. STICKY. 0x0
5 R/W Hardware Autonomous Speed Disable [HASD] When this bit is set, the LTSSM is prevented from changing the operating speed of the link, other than reducing the speed to correct unreliable operation of the link. STICKY 0x0
6 R Selectable De- emphasis [SDE] This bit selects the de-emphasis level when the Controller is operating at 5 GT/s (0 = -6 dB, 1 = -3.5 dB). This is reserved for Endpoints. 0x0
9:7 R/W Transmit Margin [TM] This field is intended for debug and compliance testing purposes only. It controls the non-de-emphasized voltage level at the transmitter outputs. Its encodings are:
  • 000: Normal operating range
  • 001: 800 - 1200 mV for full swing and 400 - 700 mV for half swing
  • 010 - 111: See PCI Express Base Specification 2.0
This field is reset to 0 when the LTSSM enters the Polling Configuration substate during link training. STICKY.		 0x0
10 R/W Enter Modified Compliance [EMC] This field is intended for debug and compliance testing purposes only. If this bit is set to 1, the device will transmit the Modified Compliance Pattern when the LTSSM enters the Polling Compliance substate.

Note:Setting this bit alone will not cause the LTSSM to enter Polling.Compliance. The Enter Compliance bit must also be set and a Hot Reset needs to be initiated by Host to enter Polling.Compliance.

STICKY.		 0x0
11 R/W Compliance SOS [CS] When this bit is set to 1, the device will transmit SKP ordered sets between compliance patterns. STICKY. 0x0
15:12 R/W Compliance De-Emphasis [CDE] This bit sets the de-emphasis level (for 5 GT/s operation) or the Transmitter Preset level (for 8 GT/s or 16 GT/s operation) when the LTSSM enters the Polling.Compliance state because of software setting the Enter Compliance bit in this register. It is used only when the link is running at 5 GT/s, 8 GT/s, or 16 GT/s. At 5 GT/s, the only valid setting are 0 (-6 dB) and 1 (-3.5 dB). STICKY. 0x0
16 R Current De- Emphasis Level [CDEL] This status bit indicates the current operating de-emphasis level of the transmitter (0 = -6 dB, 1 = -3.5 dB). This field is undefined when link is not at Gen2 speed. 0x0
17 R Equalization 8.0 GT/s Complete [EQC] This bit, when set to 1, indicates that the Transmitter Equalization procedure has completed for 8.0 GT/s. STICKY. 0x0
18 R Equalization 8.0 GT/s Phase 1 Successful [EP1S] This bit, when set to 1, indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully for 8.0 GT/s. STICKY. 0x0
19 R Equalization 8.0 GT/s Phase 2 Successful [EP2S] This bit, when set to 1, indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully for 8.0 GT/s. STICKY. 0x0
20 R Equalization 8.0 GT/s Phase 3 Successful [EP3S] This bit, when set to 1, indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully for 8.0 GT/s. STICKY. 0x0
21 R/WOCLR Link Equalization Request 8.0 GT/s [LE] This bit is Set by Controller hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. Controller hardware sets this bit if a link equalization problem is detected at the end of equalization at 8GT/s. Additionally, the Client Firmware may set this bit while requesting equalization through Local Management EP 8GTs Request Equalization Retrain Link bit. This bit is cleared by writing a 1 to this bit position by the host, or writing a 0 from the LMI. STICKY. 0x0
22 R Retimer Presence Detected [RTP] When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. 0x0
23 R Two Retimers Presence Detected [TWRTP] When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. 0x0
27:24 R Reserved [R21] Reserved 0x0
30:28 R Downstream Component Presence [DCP] DRS is not supported by the Controller and hence this field is not implemented. 0x0
31 R DRS Message Received [DMR] DRS is not supported by the Controller and hence this field is not implemented. 0x0