MSI-X Control Register @0xb0
This register contains the MSI-X configuration bits, the Capability ID for MSI-X and the pointer to the next PCI Capability Structure.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R | Capability ID [CID] |
Identifies that the capability structure is for MSI-X. This field is set by default to 11 hex. It can be re-written independently for each Function from the local management bus. |
0x11 |
| 15:8 | R | Capabilities Pointer [CP] | Contains pointer to the next PCI Capability Structure. This is set to point to the PCI Express Capability Structure at 30 hex. This can be re-written independently for each Function from the local management bus. | 8'hc0 |
| 26:16 | R | MSI-X Table Size [MSIXTS] | Specifies the size of the MSI-X Table, that is, the number of interrupt vectors defined for the Function. The programmed value is 1 minus the size of the table (that is, this field is set to 0 if the table size is 1). It can be re- written independently for each Function from the local management bus. | 11'h0 |
| 29:27 | R | Reserved [R0] | Reserved | 0x0 |
| 30 | R/W | Function Mask [FM] | This bit serves as a global mask to all the interrupt conditions associated with this Function. When this bit is set, the Controller will not send out MSI-X messages from this Function. This field can also be written from the local management bus. | 0x0 |
| 31 | R/W | MSI-X Enable [MSIXE] | Set by the configuration program to enable the MSI-X feature. This field can also be written from the local management bus. | 0x0 |