Physical Layer Configuration Register 1 @0x4
This register contains additional configured parameters at the Physical Layer of the link, and command bits for various Physical Layer functions.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R/W | Transmitted Link ID [TLI] | Link ID transmitted by the device in training sequences in the Root Port mode. | 0x0 |
| 15:8 | R/W | Transmitted FTS Count at 2.5 GT/s Speed[TFC1] | FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by thereceiver to acquire sync while exiting from L0S state. | 0x80 |
| 23:16 | R/W | Transmitted FTS Count at 5 GT/s Speed [TFC2] | FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state. | 0x80 |
| 31:24 | R/W | Transmitted FTS Count at 8 GT/s Speed [TFC3] | FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state. | 0x80 |