PCI Express Device Capabilities Register @0xc4

This register advertises the capabilities of the PCI Express device encompassing this Function.

Table 1. i_pcie_dev_cap

Bits	SW	Name	Description	Reset
2:0	R	Max Payload Size [MPS]	Specifies maximum payload size supported by the device.	3'b010
4:3	R	Phantom Functions Supported [PFS]	This field is used to extend the tag field by combining unused Function bits with the tag bits. This field is hardwired to 00 to disable this feature.	0x0
5	R	Extended Tag Field Supported [ETFS]	Set when device allows the tag field to be extended from 5 to 8 bits. It can be re-written independently for each Function from the local management bus.	0x1
8:6	R	Acceptable L0S Latency [AL0SL]	Specifies acceptable latency that the Endpoint can tolerate while transitioning from L0S to L0. It can be re-written independently for each Function from the local management bus.	0x4
11:9	R	Acceptable L1 Latency [AL1SL]	Specifies acceptable latency that the Endpoint can tolerate while transitioning from L1 to L0. It can be re-written independently for each Function from the local management bus.	0x0
14:12	R	Reserved [R1]	Reserved	0x0
15	R	Role-Based Error Reporting [RBER]	Enables role-based error reporting. It is hardwired to 1. It can be re-written independently for each Function from the local management bus.	0x01
17:16	R	Reserved [R2]	Reserved	0x0
25:18	R	Captured Slot Power Limit Value [CSPLV]	Specifies upper limit on power supplied by slot. It can be re-written independently for each Function from the local management bus.	0x0
27:26	R	Captured Power Limit Scale [CPLS]	Specifies the scale used by Slot Power Limit Value. It can be re-written independently for each Function from the local management bus.	0x0
28	R	FLR Capable [FC]	Set when device has Function-Level Reset capability. It is set by default to 1. It can be re-written independently for each Function from the local management bus.	0x01
31:29	R	Reserved [R3]	Reserved	0x0