PCI Express Device Control and Status 2 Register @0xe8
This register contains control and status bits associated with the device.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 3:0 | R/W | Completion Timeout Value [CTV] | Specifies the Completion Timeout value for the device. Allowable values are 0101 (sub-range 1) and 0110 (sub-range 2). The corresponding timeout values are stored in the local management register's Completion Timeout Interval Registers 0 and 1, respectively. Value of 0 selects completion timeout from Completion-Timeout-Interval-Registers-0 in local management register. | 0x0 |
| 4 | R/W | Completion Timeout Disable [CTD] | Setting this bit disables the Completion Timeout in the device. | 0x0 |
| 5 | R/W | ARI Forwarding Enable [AFE] | A 1 in this filed indicates that the port treats fields 7:0 of the ID as function number while converting a Type 1 config packet to type 0 config packet. | 0x0 |
| 6 | R | Atomic Op Requester Enable [AORE] | This bit must be set to enable the generation of Atomic Op Requests. If the client logic attempts to send an Atomic Op when this bit is not set, logic in the Controller will nullify the TLP on its way to the link. | 0x0 |
| 7 | R | Reserved [R18] | Reserved | 0x0 |
| 8 | R | IDO Request Enable [IRE] | When this bit is 1, the RC is allowed to set the ID- based Ordering (IDO) Attribute bit in the requests it generates. | 0x0 |
| 9 | R | IDO Completion Enable [ICE] | When this bit is 1, the RC is allowed to set the ID-based Ordering (IDO) Attribute bit in the Completions it generates. | 0x0 |
| 10 | R/W | LTR Mechanism Enable [LTRME] | This must be set to 1 to enable the Latency Tolerance Reporting Mechanism. This bit is implemented only in PF 0. Its default value is 1, but can be modified from the local management bus. This bit is read-only in PF 1. | 0x0 |
| 11 | R | Reserved [R19] | Reserved | 0x0 |
| 12 | R | 10-Bit Tag Requester Enable [T10RE] | 10bit TAGs generation are not supported in this configuration. | 0x0 |
| 14:13 | R/W | OBFF Enable [OBFFE] | Enables the Optimized Buffer Flush/Fill (OBFF) capability in the device. Valid settings are 00 (disabled), 01 (Variation A), and 10 (Variation B). | 0x0 |
| 31:15 | R | Reserved [R20] | (no description) | 0x0 |