Command and Status Register @0x4

This location contains the 16-bit Command Register and the 16-bit Status Register defined in PCI Specifications 3.0.

Table 1. i_command_status
Bits SW Name Description Reset
0 R I/O-Space Enable [IOSE] Reserved 0x0
1 R Mem-Space Enable [MSE] Reserved 0x0
2 R/W Bus-Master Enable [BME] Enables the device to issue memory requests from this Function. This field can be written from the local management bus. 0x0
5:3 R Reserved [R0] Reserved 0x0
6 R Parity Error Response Enable [PERE] Reserved 0x0
7 R Reserved [R1] Reserved 0x0
8 R SERR Enable [SE] Reserved 0x0
9 R Reserved [R2] Reserved 0x0
10 R INTx Message Disable [IMD] Reserved 0x0
18:11 R Reserved [R3] Reserved 0x0
19 R Interrupt Status [IS] Reserved 0x0
20 R Capabilities List [CL] Indicates the presence of PCI Extended Capabilities registers. This bit is hardwired to 1. 0x1
23:21 R Reserved [R4] Reserved 0x0
24 R/WOCLR Master Data Parity Error [MDPE] When the Parity Error Response enable bit in the PCI Command Register of the associated Physical Function is set, the core sets this bit when it detects the following error conditions:
  1. The core receives a Poisoned Completion TLP from the link in response to a request from this VF.
  2. The core sends out a poisoned write request on the link from this VF. (This bit remains 0 when the Parity Error Response enable bit in the PCI Command Register of the associated Physical Function is 0).
This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY.		 0x0
26:25 R Reserved [R5] Reserved 0x0
27 R/WOCLR Signaled Target Abort [STA] This bit is set when the core has sent a completion from this VF to the link with the Completer Abort status. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. 0x0
28 R/WOCLR Received Target Abort [RTA] This bit is set when this Virtual Function has received a completion from the link with the Completer Abort status. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. 0x0
29 R/WOCLR Received Master Abort [RMA] This bit is set when this VF has received a completion from the link with the Unsupported Request status. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. 0x0
30 R/WOCLR Signaled System Error [SSE] If the SERR enable bit in the PCI Command Register of the associated Physical Function is 1, this bit is set when this VF has sent out a fatal or non-fatal error message on the link to the Root Complex. If the SERR enable bit is 0, this bit remains 0. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. 0x0
31 R/WOCLR Detected Parity Error [DPE] This bit is set when the core has received a Poisoned TLP targeted at this VF. The Parity Error Response enable bit (bit 6) in the PCI Command Register of the associated PF has no effect on the setting of this bit. STICKY. 0x0