Correctable Error Mask Register @0x114

The mask bits in this register control the reporting of correctable errors. For each error type in the Correctable Error Status Register, there is a corresponding bit in this register to mask its reporting. When a mask bit is set, the occurrence of the error is not reported (by asserting the CORRECTABLE_ERROR_OUT output).

Table 1. i_corr_err_mask

Bits	SW	Name	Description	Reset
0	R	Receiver Error Mask [REM]	This bit is not implemented for Virtual Functions. Hardwired to 0.	0x0
5:1	R	Reserved [R15]	Reserved	0x0
6	R	Bad TLP Mask [BTM]	This bit is not implemented for Virtual Functions. Hardwired to 0.	0x0
7	R	Bad DLLP Mask [BDM]	This bit is not implemented for Virtual Functions. Hardwired to 0.	0x0
8	R	Replay Number Rollover Mask [RNRM]	This bit is not implemented for Virtual Functions. Hardwired to 0.	0x0
11:9	R	Reserved [R16]	Reserved	0x0
12	R	Replay Timer Timeout Mask [RTTM]	This bit is not implemented for Virtual Functions. Hardwired to 0.	0x0
13	R	Advisory Non-Fatal Error Mask [ANFEM]	This bit is not implemented for Virtual Functions. Hardwired to 0.	0x0
14	R	Corrected Internal Error Mask [CIEM]	This bit is not implemented for Virtual Functions. Hardwired to 0.	0x0
15	R	Header Log Overflow Mask [HLOM]	This bit, when set, masks the generation of error messages in response to a Header Log register overflow. STICKY. Header logs are shared across Vfs hence this field is reserved. This field is reserved since Header log sharing is selected for this configuration.	0x0
31:16	R	Reserved [R17]	(no description)	0x0