Physical Layer 16GTs Status Register @0x9cc
Physical Layer 16GTs Status Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | Equalization 16.0 GT/s Complete [EQC16] | This bit, when set to 1, indicates that the Transmitter Equalization procedure has completed for 16.0 GT/s. STICKY. | 0x0 |
| 1 | R | Equalization 16.0 GT/ s Phase 1 Successful [EP1S16] | This bit, when set to 1, indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY. | 0x0 |
| 2 | R | Equalization 16.0 GT/ s Phase 2 Successful [EP2S16] | This bit, when set to 1, indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY. | 0x0 |
| 3 | R | Equalization 16.0 GT/ s Phase 3 Successful [EP3S16] | This bit, when set to 1, indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY. | 0x0 |
| 4 | R/WOCLR | Link Equalization Request 16.0 GT/s [LE16] | This bit is Set by Controller hardware to request the 16.0 GT/s Link equalization process to be performed on the Link. Controller hardware sets this bit if a link equalization problem is detected at the end of equalization at 16GT/s. Additionally, the Client Firmware may set this bit while requesting equalization through Local Management EP 16GTs Request Equalization Retrain Link bit. This bit is cleared by writing a 1 to this bit position by the host, or writing a 0 from the LMI. STICKY. | 0x0 |
| 31:5 | R | R0 | Reserved. | 0x0 |