Low Power Debug and Control Register 2 @0xc90
This register controls internal behavior of controller for low power operations. Adjustment of this register is not required for normal operations.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 23:0 | R/W | Timeout while waiting for RX IDLE and OUTSTANDING Idle [L1TWROI] | This field enables a timeout mechanism while waiting for RX buffers and Outstanding Pkts before turning off power. Controller enters L1 substate after timeout. A value of 0x0 disables this timeout mechanism. Controller do not select internal power shutoff if it enters L1.x with this timeout. User can give timeout in micro-seconds using this register. This field is ignored if L1 substate is disabled. | 0x0 |
| 24 | R | RSVD | RSVD | 1'h0 |
| 25 | R/W | Enable outstanding CPL check [L1EOC] | Enable waiting for outstanding completions before entering L1.x. Outstanding packets expected from PCIe link as well as from AXI side is checked.FOR HAL configurations client has to assert PREVENT_L1x_ENTRY signal to prevent L1x entry. This only a tuning register. Not setting this register will cause controller to enter L1.x to save power without checking this. Controller exit from L1.x as soon as it receives expected TLps. This field is ignored if Power shutoff mechanism isselected for L1.x and Controller will always wait for outstanding packets before turning off internal power(with cpf flow). If timeout is enabled, controller enters L1.x without internal power shutoff after timeout. This bit is ignored if L1 substate is disabled. | 0x0 |
| 26 | R/W | Enable RX path check [L1ERC] | Enables waiting for RX path IDLE condition before entering L1.x. This checks that all packets from PCIE link has reached client side before entering L1.x. This only a tuning register. Not setting this register will cause controller to enter L1.x to save power without checking this. Controller will resume transferring RX data once it exit from L1.x state if RX buffers were not empty. This field is ignored if Power shutoff mechanism is enabled for L1.x and Controller will always check RX path idle condition before turning off internal power (with cpf flow). If timeout is enabled, controller enters L1.x without internal power shutoff after timeout. This bit is ignored if L1 substate is disabled. | 0x0 |
| 27 | R | RSVD | RSVD | 1'h0 |
| 28 | R | Timeout occured during RX and outstanding wait [L1TROW] | This is a debug status field. '1' in this field indicates that a timeout has occured while waiting for RX path or OUTstanding packet IDLE conditions. This is cleared on new entry to L1. | 0x0 |
| 29 | R/W | Disable Autonomous L1.x exit upon reg access [L1DAET] | L1.x turns off clocks to the controller. Default behavior is made to exit L1.x if Register access request is present at register interface. Setting this bit disables this feature. If this bit is set and CLKREQ_IN_N is 1(de-asserted), Controller responds with ERROR response to APB requests. Client can use CLIENT_EXIT_L1_SUBSTATE pin to trigger L1.x exit if autonomous exit is disabled for register access. This bit is ignored if L1 substate is disabled. | 0x1 |
| 30 | R/W | Client supplies slow clock to core during L1 [L1CSC] | L1-substate removes CORE_CLK. since the registers are implemented in core-clk, register access is not possible during L1-substate. If client can supply a slow clock to core (CORE_CLK) during L1-substates, APB/mgmt access is possiblein L1.x. set this bit if client can supply slow clock to CORE_CLK when CLKREQ_IN_N is 1(de-asserted). If this bit is set, Controller neither wake-up from L1 or generate error response for APB access during L1.x. Controller behavior is undefined if register write is performed whileslow clock is supplied to core_clk. Recommended flow is to first exit from L1-substate and perform register writes. | 0x0 |
| 31 | R | RSVD | RSVD | 1'h0 |