MSIX Function Mask Set Status 3 Register @0xd3c
This status register has one bit per function. Each function has a 1-bit MSIX Function Mask. If the function's MSIX Function Mask register is configured from 0 to 1, then the corresponding function's status bit in this register is set. Local Firmware needs to clear this register by writing a 1.
Each bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg. Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/WOCLR | VF60 MSIX Function Mask Set Status [VF60MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF60 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 1 | R/WOCLR | VF61 MSIX Function Mask Set Status [VF61MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF61 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 2 | R/WOCLR | VF62 MSIX Function Mask Set Status [VF62MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF62 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 3 | R/WOCLR | VF63 MSIX Function Mask Set Status [VF63MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF63 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 31:4 | R | Reserved [R31] | Reserved | 0x0 |