Correctable Error Status Register @0x110
This register provides the status of the various correctable errors detected by the PCI Express core. Software may clear any error bit by writing a 1 into the corresponding bit position. The states of the bits in the Correctable Error Mask Register have no effect on the status bits of this register. The setting of a correctable error status bit causes the core to generate an ERR_COR error message to the Root Complex if the error is not masked in the Correctable Error Mask Register. For errors that are not Function-specific, the error status bus is set in the registers belonging to all the Functions associated with the link, but only a single message is generated for the entire link. Header logging of received TLPs does not apply to correctable errors. All the RW1C bits can also be cleared from the local management bus by writing a 1 into the bit position.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | Receiver Error Status [RES] | This bit is not implemented for Virtual Functions. Hardwired to 0. | 0x0 |
| 5:1 | R | Reserved [R12] | Reserved | 0x0 |
| 6 | R | Bad TP Status [BTPS] | This bit is not implemented for Virtual Functions. Hardwired to 0. | 0x0 |
| 7 | R | Bad DLLP Status [BDS] | This bit is not implemented for Virtual Functions. Hardwired to 0. | 0x0 |
| 8 | R | Replay Number Rollover Status [RNRS] | This bit is not implemented for Virtual Functions. Hardwired to 0. | 0x0 |
| 11:9 | R | Reserved [R13] | Reserved | 0x0 |
| 12 | R | Replay Timer Timeout Status [RTTS] | This bit is not implemented for Virtual Functions. Hardwired to 0. | 0x0 |
| 13 | R/WOCLR | Advisory Non- Fatal Error Status [ANFES] | This bit is set when an uncorrectable error occurs, which is determined to belong to one of the special cases described in Section 6.2.3.2.4 of the PCI Express 2.0 Specifications. This causes the coreto generate an ERR_COR message in place of an ERR_NONFATAL message. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). | 0x0 |
| 14 | R | Corrected Internal Error Status [CIES] | This bit is not implemented for Virtual Functions. Hardwired to 0. | 0x0 |
| 15 | R/WOCLR | Header Log Overflow Status [HLOS] | This bit is set on a Header Log Register overflow, that is, when the header could not be logged in the Header Log Register because it is occupied by a previous header. As per SR-IOV specification, this bit is hardwired to 0 since the Header Log is Shared among VFs. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). | 0x0 |
| 31:16 | R | Reserved [R14] | Reserved | 0x0 |