ECC Correctable Error Count Register @0x218
This register contains the count of the number of ECC errors detected and corrected during reads from the PCIe core external RAMs.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R/WOCLR | PNP FIFO RAMCorrectable Error Count [PFRCER] | Number of correctable errors detected while reading from the PNP FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it. | 0x0 |
| 15:8 | R/WOCLR | SC FIFO RAMCorrectable Error Count [SFRCER] | Number of correctable errors detected while reading from the SC FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it. | 0x0 |
| 23:16 | R/WOCLR | Replay RAM Correctable Error Count [RRCER] | Number of correctable errors detected while reading from the Replay Buffer RAM. This is an 8- bit saturating counter that can be cleared by writing all 1's into it. | 0x0 |
| 31:24 | R | Reserved [R31_2] | Reserved | 0x0 |