I/O Base, I/O Limit, Secondary Status Register @0x1c
This location contains the 8-bit I/O Base Register, the 8-bit I/O Limit Register, and the 16-bit Secondary Status Registers.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | Type1 cfg I/O bar size [IOBS1] | Value set in Type1 cfg I/O bar size (bit 20 of RC BAR CONFIG register). If Type1 cfg I/O bar enable bit (bit 19 in RC BAR CONFIG register) is not set, then this field will be hard coded to 0. | 0x0 |
| 3:1 | R | Reserved [R1] | Reserved | 0x0 |
| 7:4 | R | I/O Base Register [IBR] | This field can be read and written from the local management bus if I/O BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller. | 0x0 |
| 8 | R | Type1 cfg I/O bar size [IOBS2] | Value set in Type1 cfg I/O bar size (bit 20 of RC BAR CONFIG register). If Type1 cfg I/O bar enable bit (bit 19 in RC BAR CONFIG register) is not set, then this field will be hard coded to 0. | 0x0 |
| 11:9 | R | Reserved [R2] | Reserved | 0x0 |
| 15:12 | R | I/O Limit Register [ILR] | This field can be read and written from the local management bus if I/O BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller. | 0x0 |
| 23:16 | R | Reserved [R3] | Reserved | 0x0 |
| 24 | R/WOCLR | Master Data Parity Error [MPE] | The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. Note that this bit can be set only when the Parity Error Response Enable bit is set in the Bridge Control Register | 0x0 |
| 26:25 | R | Reserved [R4] | Reserved | 0x0 |
| 27 | R/WOCLR | Signaled Target Abort [STA] | The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 28 | R/WOCLR | Recieved Target Abort [RTA] | The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 29 | R/WOCLR | Received Master Abort [RMA] | The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 30 | R/WOCLR | Received System Error [RSE] | The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 31 | R/WOCLR | Detected Parity Error [DPE] | The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |