PASID Capability Header @0x444

PASID Capability Header fields are described below:

Table 1. i_pasid_cap_reg

Bits	SW	Name	Description	Reset
0	R	Reserved [RSVD1]	These bits are currently reserved. These are implemented as register bits that can be read and written by the host through a Config transaction, or via the local management interface.	0x0
1	R	Execute Permission Supported [EXPS]	If set, the Endpoint supports sending memory requests that have the Execute Requested bit set. If clear, the Endpoint should never set the Execute Requested bit.	0x1
2	R	Priveleged Mode Supported [PRMS]	If set, the Endpoint supports operating in Privileged and Non-Privileged modes, and supports sending requests that have the Privileged Mode Requested bit set. If clear, the Endpoint should never set the Privileged Mode Requested bit.	0x1
7:3	R	Reserved [RSVD2]	These bits are currently reserved. These are implemented as register bits that can be read and written by the host through a Config transaction, or via the local management interface.	0x0
12:8	R	Max PASID Width [MPSW]	Indicates the width of the PASID field supported by the Endpoint. The value indicates support for PASID values 0 through 2n-1 (inclusive). The value 0 indicates support for a single PASID (0). The value 20 indicates support for all PASID values (20 bits). This field must be between 0 and 20 (inclusive).	0x14
15:13	R	Reserved [R15]	Reserved	0x0
16	R/W	PASID Enable [PASE]	If set, the Endpoint is permitted to send and receive TLPs that contain a PASID TLP Prefix. If clear, the Endpoint is not permitted to do so.	0x0
17	R/W	Execute Permission Enable [EXPE]	If set, the Endpoint is permitted to send requests that have the Execute Requested bit set. If clear, the Endpoint is not permitted to do so.	0x0
18	R/W	Privileged Mode Enable [PRME]	If set, the Endpoint is permitted to send requests that have the Privileged Mode Requested bit set. If clear, the Endpoint is not permitted to do so.	0x0
31:19	R	Reserved [R31]	Reserved	0x0