PIPE FIFO Latency Control Register @0x368

This is register includes bits to control pipe FIFO latency

Table 1. i_pipe_fifo_latency_ctrl_reg

Bits	SW	Name	Description	Reset
0	R/W	Disable PIPE TX FIFOCentering on Empty [DPTFCE]	By default, if FIFO empty is reached, the PIPE TX FIFO accumulates two entries before reading the FIFO again. This is to prevent FIFO from reaching empty again. This bit must remain at 0 to allow the PIPE TX FIFO to recover effectively from a Empty condition.	0x0
1	R/W	Reserved [DPRFLR]	Reserved. Must be 1'b1 for functional mode.	0x1
14:2	R	Reserved [R14]	Reserved	0x0
15	R/W	Disable PIPE TX FIFO Write Idle Filter [DPTFWF]	This bit can be used to prevent PIPE_TX_FIFO from reaching full during TX Electrical Idle. 0: During TX Electrical Idle, the PIPE_TX_FIFO is kept at half fill level by filtering the writes into the PIPE_TX_FIFO. 1: The PIPE_TX_FIFO write filtering logic is turned off. Default value of this bit is 1.	0x1
31:16	R	Reserved [R31]	Reserved	0x0