MSI Control Register @0x90
This register is used only when the core is configured to support Message Signaled Interrupts (MSIs). In addition to the MSI control bits, this location also contains the MSI Capability ID and the pointer to the next PCI Capability Structure.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R | Capability ID [CID] | Specifies that the capability structure is for MSI. Hardwired to 05 hex. | 0x05 |
| 15:8 | R | Capabilities Pointer [CP] | Pointer to the next PCI Capability Structure. The value read from this read-only field is the corresponding pointer in the MSI Capability Structure of the Physical Function this VF is attached to. The setting is common across all the Virtual Functions. | 8'hb0 |
| 16 | R/W | MSI Enable [ME] | Set by the configuration program to enable the MSI feature. This field can also be written from the local management bus. | 0x0 |
| 19:17 | R | Multiple Message Capable [MMC] | Encodes the number of distinct messages that the core is capable of generating for this Function (000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32). Thus, this field defines the number of the interrupt vectors for this Function. The core allows up to 32 distinct messages, but the setting of this field must be based on the number of interrupt inputs of the core that are actually used by the client. For example, if the client logic uses eight of the 32 distinct MSI interrupt inputs of the core for this Function, then the value of this field must be set to 011. This field can be written from the local management bus. | 0x0 |
| 22:20 | R/W | Multiple Message Enable [MME] | Encodes the number of distinct messages that the core is programmed to generate for this Function (000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32). This setting must be based on the number of interrupt inputs of the core that are actually used by this Function. This field can be written from the local management bus. | 0x0 |
| 23 | R | 64-Bit Address Capable [AC64] | Set to 1 to indicate that the device is capable of generating 64-bit addresses for MSI messages. | 0x1 |
| 24 | R | MSI masking capable [MC] | Can be modified using localmanagement interface | 0x1 |
| 31:25 | R | Reserved [R0] | Reserved | 0x0 |