Link Equalization Control 2 Register @0xe60
This register implements fields to control and override Link Equalization.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/W | Gen3 EQ Phase2 Remote Tx Preset Enable [G3PRRMEN] | Used only in EP Mode. This bit enables the Controller, to feedback a Tx Preset for the Remote end Transmitter in the first iteration of Link Equalization Phase2 at Gen3 speed. The Gen3 Tx Preset that is used for feedback is programmable in bits [4:1] of this register. Reserved for RP Mode. | 0x0 |
| 4:1 | R/W | Gen3 EQ Phase2 Remote Tx Preset [G3RMTXPR] | Used only in EP Mode. When enabled using bit-0, this Tx Preset will be transmitted in TS1s for the Remote end Transmitter in the first iteration of Gen3 Equalization Phase2. Reserved for RP Mode. | 0x0 |
| 5 | R/W | Gen3 Local Override Tx Preset Enable [G3OVRREN] | This is a debug bit. Can be used in both EP and RP Mode. If enabled, the Controller locally applies the Gen3 Local Override Tx Presetto the Local Transmitter throughout Gen3. The Controller performs the Override Preset to Coefficient mapping and then drives on PIPE_TX_DEEMPHASIS signal on the PIPE Interface. | 0x0 |
| 9:6 | R/W | Gen3 Local Override Tx Preset[G3OVRRPR] | This is a debug register field. Can be used in both EP and RP Mode. When enabled using bit-5, this Tx Preset will be applied to the local Transmitter throughout Gen3 regardless of Gen3 Equalization. | 0x0 |
| 10 | R/W | Gen4 EP 8GTEQ TS2 Enable [G4EQTSEN] | Used only in EP Mode. During Gen3 to Gen4 Speed Change negotiation, this bit enables the Controller in EP Mode to transmit 8G EQ TS2 in Recovery.Rcvr.Cfg state instead of standard TS2 as defined in PCIe specification. The Tx Preset that will be used in the 8GT EQ TS2 is programmable in bits [15:12] of this register. | 0x0 |
| 11 | R/W | Gen4 EQ Phase2 Remote Tx Preset Enable [G4PRRMEN] | Used only in EP Mode. This bit enables the Controller, to feedback a Tx Preset for the Remote end Transmitter in the first iteration of Link Equalization Phase2 at Gen4 speed. The Gen4 Tx Preset that is used for feedback is programmable in bits [15:12] of this register. | 0x0 |
| 15:12 | R/W | Gen4 EQ Phase2 Remote Tx Preset [G4RMTXPR] | Used only in EP Mode. If enabled, this Tx Preset will be transmitted in 8G EQ
TS2s during Gen3 to Gen4 Speed Change negotiation. Also, if enabled, this Tx Preset
will be transmitted in TS1s in the first iteration of Gen4 Equalization Phase2. Note: If the Remote end device advertised the same preset at start of Equalization Phase2, then this Preset will be skipped. |
0x0 |
| 16 | R/W | Gen4 Local Tx Preset Override Enable [G4OVRREN] | This is a debug bit. Can be used in both EP and RP Mode. If enabled, the Controller locally applies the Gen4 Local Override Tx Presetto the Local Transmitter throughout Gen4. The Controller performs the Override Preset to Coefficient mapping and then drives on PIPE_TX_DEEMPHASIS signal on the PIPE Interface. | 0x0 |
| 20:17 | R/W | Gen4 Local Override Tx Preset [G4OVRRPR] | This is a debug register field. Can be used in both EP and RP Mode. When enabled using bit-16, this Tx Preset will be applied to the local Transmitter throughout Gen4 regardless of Gen4 Equalization. | 0x0 |
| 31:21 | R | Reserved [R21] | Reserved | 0x0 |