Equalization Debug Monitor Control Register @0xe4c

The register bits to Control EQ debug Monitor operation are implemented in this Register.

Table 1. i_eq_debug_mon_control_reg
Bits SW Name Description Reset
0 R/W Clear All capture [CLRCAPT] Setting this bit clears all captured information in the EQ Debug Status Registers. If it is unset then capture is allowed in status registers. 0x0
4:1 R/W Capture Lane Select [CAPTLNSEL] Selects the Lane whose Equalization Debug information is to be captured. Please note, this signifies the physical lane number. 0x0
6:5 R/W Capture EQ Phase Select [CAPTPHSEL] Selects the Equalization Phase when capture is to be done.
  • 01 : Phase 2,
  • 10 : Phase 3,
  • 11 : Phase 0, 1, 2, and 3.
 0x3
9:7 R/W Capture EQ Speed Select [CAPTSPDSEL] Selects the Link Speed at which capture is to be done.
  • 000 : Any speed,
  • 001 : Gen 3,
  • 010 : Gen 4,
  • 100 : Gen 5.
 0x0
10 R Eq Debug Capture Behavior [CAPTBEH] If this is set , the first 64 equalization info events are captured else the last 64 events are captured 0x1
31:11 R Reserved [R1] Reserved 0x0