SRIS Control Register @0x74

This register contains control bits to enable the SRIS operation in the PHY Layer

Table 1. i_sris_control_reg

Bits	SW	Name	Description	Reset
0	R/W	SRIS Enable [SRISE]	Setting this bit enables SRIS mode in the PHY layer. This bit should be changed before link training begins by holding theLINK_TRAINING_ENABLE input to 1'b0. When SRIS is disabled using this bit the Lower SKP OS Generation Supported Speeds Vector and Lower SKP OS Reception Supported Speeds Vector in the Link Capabilities Register 2 will be forced to ZERO. The default value of this register can be controlled using the SRIS_ENABLE strap input.	0x0
31:1	R	Reserved [R31]	Reserved	0x0