PM_CLK Frequency Register @0x140

This register should be programmed with the frequency of the PM_CLK input to the Controller. The Controller supports the frequency range of 2 MHz to 60 MHz for PM_CLK. The reset value reflects the PM_CLK frequency chosen during Controller configuration.

NOTE: PM_CLK will be timed at 60 Mhz and the Controller SDC file will be generated accordingly. If timing is to be closed at a different frequency, then the user needs to update the SDC accordingly.

Table 1. i_pm_clk_frequency_reg

Bits	SW	Name	Description	Reset
7:0	R/W	PM_CLKFrequency Select [PMCLKFRQ]	This field specifies the PM_CLK Frequency selected. The encoding is described below: 000000: Reserved 000001: Reserved 000010: PM_CLK is 2 MHz 000011: PM_CLK is 3 MHz 000100: PM_CLK is 4 MHz 000101: PM_CLK is 5 MHz 111010: PM_CLK is 58 MHz 111011: PM_CLK is 59 MHz 111100: PM_CLK is 60 MHz 111101: Reserved 111110: Reserved 111111: Reserved	8'd25
31:8	R	Reserved [R0]	Reserved	0x0