Link Control and Status Register @0xd0

This register contains control and status bits specific to the PCI Express link.

Table 1. i_link_ctrl_status
Bits SW Name Description Reset
1:0 R/W Active State Power Management Control [ASPMC] Controls the level of ASPM support on the PCI Express link associated with the function. The valid setting are:
  • 00: ASPM disabled
  • 01: L0s entry enabled, L1 disabled
  • 10: L1 entry enabled, L0s disabled
  • 11: Both L0s and L1 enabled
Note that the ASPM Control bits can be enabled only if the corresponding ASPM Support[1:0] bit is 1 in the Link Capabilities Register.		 0x0
2 R Reserved [R10] Reserved 0x0
3 R Read Completion Boundary [RCB] Indicates the Read Completion Boundary of the Root Port (0 = 64 bytes, 1 = 128 bytes). This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x0
4 R/W Link Disable [LD] Writing a 1 to this bit position causes the LTSSM to go to the Disable Link state. The LTSSM stays in the Disable Link state while this bit is set. 0x0
5 R Retrain Link [RL] Setting this bit to 1 causes the LTSSM to initiate link training. This bit always reads as 0. This bit can be set by Host SW at any time independent of the LTSSM state. If the LTSSM is not in L0 state, the Controller will internally register the retrain command and initiate the link retrain immediately after the LTSSM reaches L0. For example, if the LTSSM is already in Recovery, the Controller will initiate Retrain Link after the LTSSM transitions back to L0 state. 0x0
6 R/W Common Clock Configuration [CCC] A value of 0 indicates that the reference clock of this device is asynchronous to that of the upstream device. A value of 1 indicates that the reference clock is common. 0x0
7 R/W Extended Synch [ES] Set to 1 to extend the sequence of ordered sets transmitted while exiting from the L0S state. 0x0
8 R Enable Clock Power Management [ECPM] This field is hardwired to 0 when the Controller is in the RC mode. 0x0
9 R/W Hardware Autonomous Width Disable [HAWD] When this bit is set, the local application must not request to change the operating width of the link, other than attempting to correct unreliable Link operation by reducing Link width. 0x0
10 R/W Link Bandwidth Management Interrupt Enable [LBMIE] When Set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered. Hardwired to 0 if Link Bandwidth Notification Capability is 0. 0x0
11 R/W Link Autonomous Bandwidth Interrupt Enable [LABIE] When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered. Hardwired to 0 if Link Bandwidth Notification Capability is 0. 0x0
15:12 R Reserved [R11] Reserved 0x0
19:16 R Negotiated Link Speed [NLS] Negotiated link speed of the device. The only supported speed IDs are 2.5 GT/s per lane (0001), 5.0 GT/s per lane (0010), 8.0 GT/s per lane (0011), and 16.0 GT/s per lane (0100). 0x1
25:20 R Negotiated Link Width [NLW] Set at the end of link training to the actual link width negotiated between the two sides. 0x4
26 R Reserved [R12] Reserved 0x0
27 R Link Training Status [LTS] This bit is set to 1 when the LTSSM is in the Recovery or Configuration states, or if a 1 has been written to the Retrain Link bit but the link training has not yet begun. 0x0
28 R Slot Clock Configuration [SCC] Indicates that the device uses the reference clock provided by the connector. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x0
29 R Data Link Layer Active [DA] Indicates the status of the Data Link Layer. Set to 1 when the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0 in this version of the Controller. 0x0
30 R/WOCLR Link Bandwidth Management Status [LBMS] This bit is Set by hardware to indicate that either link training has completed following write to retrain link bit, or when HW has changed link speed or width to attempt to correct unreliable link operation. This triggers an interrupt to be generated through PHY_INTERRUPT_OUT if enabled. Hardwired to 0 if Link Bandwidth Notification Capability is 0. 0x0
31 R/WOCLR Link Autonomous Bandwidth Status [LABS] This bit is Set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation. This triggers an interrupt to be generated through PHY_INTERRUPT_OUT if enabled. Hardwired to 0 if Link Bandwidth Notification Capability is 0. 0x0