Local Error and Status 2 Register @0xd00

This is an extension of the Local Error and Status Register. This register contains the status of the various events, errors and abnormal conditions in the Controller. Any of the status bits can be reset by writing a 1 into the bit position. Unless masked by the setting of the Local Interrupt Mask 2 Register, the occurrence of any of these conditions causes the Controller to activate the LOCAL_INTERRUPT output.

Table 1. i_local_error_status_2_register
Bits SW Name Description Reset
0 R/WOCLR MSI Mask Cleared Status [MSIMSKCLST] This status bit indicates that one or more bits of MSI Mask of any function, PF or VF, was programmed or configured from 1 to 0 by local firmware or host software. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the user in debug_mux_control_2_reg. When this status bit is set, the PCIe Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg. Note that this is a Read Only Status bit. The MSI Mask Clear status per-function is captured in the msi_mask_cleared_status_register. Firmware has to clear the per-function bits in msi_mask_cleared_status_register to clear this status bit and to deassert LOCAL_INTERRUPT. 0x0
1 R/WOCLR MSI Mask Set Status [MSIMSKSETST] This status bit indicates that one or more bits of MSI Mask of any function, PF or VF, was programmed or configured from 0 to 1 by local firmware or host software. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg. Note that this is a Read Only Status bit. The MSI Mask Clear status per-function is captured in the msi_mask_set_status_register. Firmware has to clear the per-function bits in msi_mask_set_status_register to clear this status bit and to deassert LOCAL_INTERRUPT. 0x0
2 R/WOCLR MSIX Function Mask Cleared Status [MSIXMSKCLST] This status bit indicates that the MSIX Function Mask of any function, PF or VF, was programmed or configured from 1 to 0 by local firmware or host software. This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the user in debug_mux_control_2_reg. When this status bit is set, the PCIe Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg. Note that this is a Read Only Status bit. The MSIX Function Mask Clear status per-function is captured in the msix_function_mask_cleared_status_register. Firmware has to clear the per-function bits in msix_function_mask_cleared_status_register to clear this status bit and to deassert LOCAL_INTERRUPT. 0x0
3 R/WOCLR MSIX Function Mask Set Status [MSIXMSKSETST] This status bit indicates that the MSIX Function Mask of any function, PF or VF, was programmed or configured from 0 to 1 by local firmware or host software. This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg. Note that this is a Read Only Status bit. The MSIX Function Mask Clear status per-function is captured in the msix_function_mask_set_status_register. Firmware has to clear the per-function bits in msix_function_mask_set_status_register to clear this status bit and to deassert LOCAL_INTERRUPT. 0x0
4 R/WOCLR Invalid SW Margining Command Received [ISWMCR] This bit validates the 16-bit command stored in bits [15:0] and the Lane Number stored in bits [19:16] of the margining_error_status1_reg register. This bit is set upon receiving the first Error. Local firmware must clear this bit by writing a 1 to this bit before another error can be logged in the margining_error_status1_reg register. 0x0
5 R/WOCLR Invalid PHY Margining Command Received [IPHYMCR] This bit validates the 8-bit command stored in bits [7:0] and the Lane Number stored in bits [11:8] of the margining_error_status1_reg register. This bit is set upon receiving the first Error. Local firmware must clear this bit by writing a 1 to this bit before another error can be logged in the margining_error_status1_reg register. 0x0
6 R/WOCLR Write Ack Wait Timeout Error [WAWTE] This bit indicates that the Controller detected a 10 ms timeout while waiting for Write Ack Lane Margining response from a PHY. The lane on which this timeout was detected is captured in bits 17:14 of the margining_error_status2_reg register. This bit is set upon receiving the first Error. Local firmware must clear this bit by writing a 1 to this bit before another error can be logged in the margining_error_status2_reg register. 0x0
7 R/WOCLR Unexpected PHY Response Received [UPRR] This bit indicates that the Controller received an unexpected PHY Response for Lane Margining. The lane on which this error was detected is captured in bits 21:18 of the margining_error_status2_reg register. Unexpected PHY Response is detected by Controller if PHY writes to the Margin Status or the Margin NAK bits of the MAC RX Margin Status 0 Register when no change in Start Margin or Margin Offset issued by Controller or after the Write Ack Wait Timeout. This bit is set upon receiving the first Error. Local firmware must clear this bit by writing a 1 to this bit before another error can be logged in the margining_error_status2_reg register. 0x0
8 R/WOCLR NFTSTimeout Status [NFTSTOS] This status bit indicates that a NFTS Timeout occured. This could occur if the PHY failed to achieve lock on the receive data before the NFTS Timeout during Rx_L0s.FTS state. Local firmware should consider increasing the advertized NFTS values if this event occurs. 0x0
9 R Reserved [R9] Reserved. 0x0
10 R Reserved [R10] Reserved. 0x0
11 R/WOCLR Split Completion Table byte count RAM uncorrectable error [UNCESCBYTE] This status bit indicates that the Controller detected an uncorrectable error in the Split Completion Table byte count RAM. 0x0
12 R/WOCLR Split Completion Table Timer RAM uncorrectable error [UNCESCTIMER] This status bit indicates that the Controller detected an uncorrectable error in the Split Completion Table Timer RAM. 0x0
13 R/WOCLR Split Completion Table State RAM uncorrectable error [UNCESCSTATE] This status bit indicates that the Controller detected an uncorrectable error in the Split Completion Table State RAM. 0x0
14 R/WOCLR Link Equalization Request Interrupt [LEQRQIN] EP Mode: Indicates that the Controller hardware detected a problem with equalization and automatically requested for equalization redo at the end of the equalization. Controller checks for problems in Recovery.Rcvr.Lock stateby comparing the Tx Coefficients agreed at end of Eq Phase2 with the Tx Coefficients received in TS1s in Recovery.Rcvr.Lock state at the end of equalization. Any mismatch is detected and the Request Equalization bit is set in Recovery.Rcvg.Cfg. This bit is set for 8GT/s, 16GT/s equalization requests.
  1. The Link Eq Request 8GT/s bit-5 in Link Status 2 Register will be set for 8GT/s Eq Request.
  2. The Link Eq Request 16.0 GT/s, bit-4 in 16.0 GT/s Status Register will be set for 16GT/s EqRequest.
RC Mode: Indicates that the Controller received Equalization Request from downstream component. This bit is set for both 8GT/s and 16GT/s equalization requests.
  1. The Link Eq Request 8GT/s bit-5 in Link Status 2 Register will be set for 8GT/s Eq Request.
  2. The Link Eq Request 16.0 GT/s, bit-4 in 16.0 GT/s Status Register will be set for 16GT/s Eq Request.
 0x0
15 R Reserved [R15] Reserved. 0x0
16 R LTSSM State Transition Interrupt Status [LSTINT] Indicates that one or more LTSSM Transitions, that were programmed for firmware monitor/ control has occured. This is a Read-Only Status bit. To process the LTSSM State Transition Interrupt, the FW must go through the following steps:
  1. Read LTSSM Transition Debug Status Register (i_ltssm_transition_debug_stat_reg) to determine the LTSSM Transition event that occured.
  2. Process the LTSSM Transition event and clear by writing a 1 to (i_ltssm_transition_debug_stat_reg).
0x0
17 R FC Timeout Error Status [FTE] Assered when Flow control timer cross the limit value. FC Timeout Error causes link to retrain. 0x0
31:18 R Reserved [R17] Reserved. 0x0