Uncorrectable Error Status Register @0x104

This register provides the status of the various uncorrectable errors detected by the PCI Express core. Software may clear any error bit by writing a 1 into the corresponding bit position. The states of the bits in the Uncorrectable Error Mask Register have no effect on the status bits of this register. The setting of an uncorrectable error status bit causes the core to generate an ERR_FATAL message if the corresponding severity bit of the Uncorrectable Error Severity Register is 1. If the severity bit is 0, however, there are two separate ways the error could be processed:
  • In certain cases, the uncorrectable error is treated as an Advisory Non-Fatal Error. These cases are treated as similar to correctable errors, causing the core to generate an ERR_COR message instead of an ERR_NONFATL message. For details on these special cases, refer to Section 6.2.3.2.4 of the PCI Express Base Specifications, Version 1.1.
  • In all other cases, the core sends an ERR_NONFATAL message when the error is detected. In all cases, the sending of the error message can be suppressed by setting the bit corresponding to the error type in the Uncorrectable Error Mask Register.

For errors that are not Function-specific, the error status bus is set in the registers belonging to all the Functions associated with the link, but only a single message is generated for the entire link. In the case of certain errors detected by the Transaction Layer, the associated TLP header is logged in the Shared VF Header Log Registers. All the RW1C bits can also be cleared from the local management bus by writing a 1 into the bit position.If error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted, f/w will be allowed to write into AER uncorrectable Error status register).

Table 1. i_uncorr_err_status
Bits SW Name Description Reset
3:0 R Reserved [R0] Reserved 0x0
4 R Data Link Protocol Error Status [DLPER] This bit is not implemented for Virtual Functions. Hardwired to 0. 0x0
11:5 R Reserved [R1] Reserved 0x0
12 R/WOCLR Poisoned TLP Status [PTS] This bit is set when the core receives a poisoned TLP from the link, targeted at this VF. This error is Function-specific. This error is considered non-fatal by default. The error is reported by sending an ERR_NONFATAL message. The header of the received TLP with error is logged in the Shared VF Header Log Registers associated with the VF. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
13 R Flow Control Protocol Error Status [FCPES] This bit is is not implemented for Virtual Functions. Hardwired to 0. 0x0
14 R/WOCLR Completion Timeout Status [CTS] This bit is set when the completion timer associated with an outstanding request times out. This error is Function-specific. This error is considered non-fatal by default. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
15 R/WOCLR Completer Abort Status [CAS] This bit is set when the core has returned the Completer Abort (CA) status to a request received from the link. This error is Function-specific. The header of the received request that caused the error is logged in the Shared VF Header Log Registers. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
16 R/WOCLR Unexpected Completion Status [UCS] This bit is set when the core has received an unexpected Completion packet from the link. This error is not Function-specific. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted). 0x0
17 R Receiver Overflow Status [Rcvr_Overflow_Status] This bit is not implemented for Virtual Functions. Hardwired to 0. 0x0
18 R Malformed TLP Status [Malformed_TLP_Status] This bit is not implemented for Virtual Functions. Hardwired to 0. 0x0
19 R ECRC Error Status [ECRC_Err_Status] This bit is not implemented for Virtual Functions. Hardwired to 0. 0x0
20 R/WOCLR Unsupported Request Error Status [URES] This bit is set when the core has received a request from the link that it does not support. This error is not Function-specific. This error is considered non-fatal by default. In the special case described in Sections 6.2.3.2.4.1 of the PCI Express Specifications, the error is reported by sending an ERR_COR message. In all other cases, the error is reported by sending an ERR_NONFATAL message. The header of the received request that caused the error is logged in the Shared VF Header Log Registers. STICKY. F/w will be allowed to write into this error status field when error emulation emulation feature is enabled (i.e., if bit12 of Debug MUX Control 3 register is asserted. 0x0
21 R Reserved [R2] Reserved 0x0
22 R Uncorrectable Internal Error Status [Uncorr_Int_Err_Status] This bit is not implemented for Virtual Functions. Hardwired to 0. 0x0
31:23 R Reserved [R3] Reserved 0x0