Interrupt Line and Interrupt Pin Register @0x3c
This location contains the PCI 3.0 Interrupt Line and Interrupt Pin Registers. These registers are used only when the Controller is configured to support PCI legacy interrupts. If the legacy interrupt mode is configured, the Controller receives interrupt indications from the client logic on its INTA_IN, INTB_IN, INTC_IN and INTD_IN inputs, and sends out Assert_INTx or Deassert_INTx messages on the link in response to their activation or deactivation, respectively. The Interrupt Pin Register defines which of the four inputs is connected to the Function corresponding to this register set. The Interrupt Line register defines the input of the interrupt controller (IRQ0 - IRQ15) in the Root Complex that is activated by each Assert_INTx message.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R/W | Interrupt Line Register [ILR] | Identifies the IRQx input of the interrupt controller at the Root Complex that is activated by this Functions interrupt (00 = IRQ0, ... , 0F = IRQ15, FF = unknown or not connected). This field is writable from the local management bus. | 8'hff |
| 10:8 | R | Interrupt Pin Register [IPR] | Identifies the interrupt input (A, B, C, D) to which this Functions interrupt output is connected to (01 = INTA, 02 = INTB, 03 = INTC, 04 = INTD). The assignment of interrupt inputs to Functions is fixed when the Controller is configured. This field can be re-written independently for each Function from the local management bus. | 0x1 |
| 31:11 | R | Reserved [R16] | Reserved | 0x0 |