MSI Mask Register @0xa0

This register contains the MSI mask bits, one for each of the interrupt levels.

Table 1. i_msi_mask

Bits	SW	Name	Description	Reset
0	R/W	MSI Mask [MM]	Mask bits for MSI interrupts. The Multiple Message Capable field of the MSI Control Register specifies the number of distinct interrupts for the Function, which determines the number of valid mask bits. Please note that if the Multiple Message Capable field is changed from the local management APBbus then the width of the MSI Mask field also changes correspondingly	0x0
31:1	R	Reserved [R0]	Please note that if the Multiple Message Capable field is changed from the local management APBbus then the width of this field also changes correspondingly	0x0