Gen 4 Link Equalization Debug Register @0x3cc

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN4 Link Equalization. When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen4 Equalization Phase 3. When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen4 Equalization Phase 2.

Table 1. i_gen4_link_eq_debug_status_reg_lane3
Bits SW Name Description Reset
3:0 R Link Equalization TX Preset [LEQTXPR] TX Preset agreed upon for this lane. 0x8
4 R Link Equalization TX Preset Valid [LEQTXPRV] TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2. 0x0
7:5 R Reserved [RES75] Reserved 0x0
25:8 R Link Equalization TX Coefficient [LEQTXCO] TX Coefficients agreed upon for this lane.
  • [25:20] : Post Cursor Coefficient
  • [19:14] : Cursor Coefficient
  • [13:8] : Pre-Cursor Coefficient
 18'b00011010000100011
31:26 R Reserved [RES3126] Reserved 0x0