Debug Mux Control Register @0x208

Table 1. i_debug_mux_control_reg
Bits SW Name Description Reset
4:0 R/W Reserved Reserved 0x0
6:5 R Reserved [R6] Reserved 0x0
7 R/W Reserved [R77] This bit should be set to 0 for backward compatibility. 0x0
8 R Reserved [R88] Reserved 0x0
9 R/W MSI Vector Count Mode Select [MSIVCMS] Sets the mode of generating MSI_VECTOR_COUNT output for all functions. 0 - MSI_VECTOR_COUNT always outputs the configured value of MSI Multiple Message Enable[2:0] register. 1 - MSI_VECTOR_COUNT outputs the lesser of the MSI Multiple Message Enable[2:0] and MSI Multiple Message Capable[2:0] This mode can be used to handle any programming error form the Host software. 0x0
10 R/W Disable RX NP Starvation Prevention [DRXNPSP] As per PCIe specification, Non-Posted packets should not pass ahead of a Posted packet. Posted and Non-Posted packets are stored in a common Receive PNP FIFO. Controller ensures that the P and NP are delivered to the HAL/AXI target interface without violating the Ordering rules. When a mix of P and NP requests are received over the link, the NP packets can be starved if multiple Posted packets are stored in the PNP RX FIFO. Controller implements a mechanism to prevent NP Starvation Prevention which can be programmed through this bit:
  • 0: Send P and NP in the received order, instead of giving priority only for P and starve NP when continous P, NP packets are received.
  • 1: Priority only for P. Starve NP when continous P, NP packets are received.
NP packets sent to HAL/AXI target interface only when all P packets in the PNP FIFO are delivered.		 0x0
11 R/W Disable Client TX MUXarbitartion [R1111] When this bit is 1, Disable Client TX MUX Completion and PNP request arbitartion,roundrobin priority logic addedto prevent PNP requests from starving when completions are present. 0x0
12 R Reserved [R1212] Reserved 0x0
13 R Reserved [R1313] Reserved 0x0
14 R/W Disable Set Slot Power Limit Message [DSSPLM] Disable sending Set Slot Power Limit Message if the Slot Capabilitied register is configured. 0x0
15 R/W Force Disable Scrambling [FDS] Disable Scrambling/Descrambling in Gen1/Gen2. 0x0
16 R/W Enable AXI Bridge Write Priority [AWRPRI] When this bit is 1, the AXI bridge places a write request on the HAL Master interface in preference over a read request if both AXI write and AXI read requests are available to be asserted on the same clock cycle. 0x0
17 R/W Disable Parity Check [HPRSUPP] When this bit is 1, data path parity check is disabled on the TX side of the Controller. 0x0
18 R/W Disable OS After Skip Framing Check [DOASFC] When this bit is 1, the Controller will not check for OS after SKIP OS as part of Gen3 Framing Error Checks. This bit should normally set to 0, as thisis a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications. 0x0
19 R/W Disable Illegal OS After EDS Framing Check [DIOAEFC] When this bit is 1, the Controller will not check for illegal OS after EDS as part of Gen3 Framing Error Checks. This bit should normally set to 0, as thisis a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications. 0x0
20 R/W Disable checking of invalidmessage codes [DCIVMC] When this bit is 1, the Controller will not check for invalid message codes. This bit should normally set to 0, as the invalid message code checking is mandatory in the PCIe 3.0 specifications. 0x0
21 R/W Disable Sync Header Error Check [DSHEC] When this bit is 0, the Controller will signal a framing error if it detects a sync header error in the received blocks at 8 GT/s or 16 GT/s speed (A 00 or 11 binary setting of the sync header on the received blocks in any lane constitutes a framing error). Setting this bit to 1 suppresses this error check. This bit should normally be set to 0, as the sync header check is mandatory in the PCIe 3.0 Specifications. 0x0
22 R/W Disable Link Re-Training on Framing Error [DLRFE] When this bit is 1, the Controller will not transition its LTSSM into the Recovery state when it detects a Framing Error at 8 GT/s or 16 GT/s speed (as defined in Section 4.2.2.3.3 of the PCIe Base Specification 3.0. This bit must normally be set to 0 so that a Framing Error will cause the LTSSM to enter Recovery. The setting of this bit has no effect on the operation of the Controller at 2.5 and 5 GT/s speeds. 0x0
23 R/W Disable Link Upconfigure Capability [DLUC] The user may set this bit to turn off the link upconfigure capability of the Controller. Setting this bit prevents the Controller from advertising the link upconfigure capability in training sequences transmitted in the Configuration.Complete state. In addition, setting this bit causes the Controller to put the unused lanes into Turn Off mode.
When disable_link_upconfigure_capability==1: Controller drives PIPE_TX_ELEC_IDLE==1 AND PIPE_TX_COMPLIANCE==1 for the Unused upper lanes. The Unused upper lanes are put into Turn Off mode by the PHY as per PIPE specification.
When disable_link_upconfigure_capability==0:Controller drives PIPE_TX_ELEC_IDLE==1 AND PIPE_TX_COMPLIANCE==0 for the Unused upper lanes. The Unused upper lanes are put into Electrical Idle by the PHY.
 0x0
24 R/W Enable Fast Link Training [EFLT] This bit is provided to shorten the link training time to facilitate fast simulation of the design, especially at the gate level. Enabling this bit has the following effects:
  • The 1 ms, 2 ms, 12 ms, 24 ms, 32 ms, and 48 ms timeout intervals in the LTSSM are shortened by a factor of 500.
  • In the Polling.Active state of the LTSSM, only 16 training sequences are required to be transmitted (Instead of 1024) to make the transition to the Configuration state.
This bit should not be set during normal operation of the Controller.		 0x0
25 R/W Enable Slot Power Capture [ESPC] When this bit is set to 1, the Controller will capture the Slot Power Limit Value and Slot Power Limit Scale parameters from a Set_Slot_Power_Limit message received in the Device Capabilities Register. When this bit is 0, the capture is disabled. This bit is valid only when the Controller is configured as an Endpoint. It has no effect when the Controller is a Root Complex. 0x0
26 R/W Inject End-to-End Data Protection Parity Error [IEDPPE] When set to 1, this bit inverts the parity bits generated by the Controller for end-to-end data protection. This will result in the inversion of parity bits for data payloads delivered through the HAL Target Interface request descriptor. This bit is to be used for diagnostics only, and should not be set during normal operation. 0x0
27 R/W Disable Gen3 LFSR Update from SKP [DGLUS] Setting this bit to 1 disables the update of the LFSRs in the Gen3 descramblers of the Controller, from the values received in SKP sequences. This bit should not be set during normal operation, but is useful for testing. 0x0
28 R/W Disable Electrical Idle Infer in L0 State [DEI] Setting this bit to 1 disables the inferring of electrical idle in the L0 state. Electrical idle is inferred when no flow control updates and no SKP sequences are received within an interval of 128 μs. This bit should not be set during normal operation, but is useful for testing. 0x0
29 R/W Disable Flow Control Update Timeout [DFCUT] When this bit is 0, the Controller will time out and re-train the link when no Flow Control Update DLLPs are received from the link within an interval of 128 μs. Setting this bit to 1 disables this timeout. When the advertised receive credit of the link partner is infinity for the header and payload of all credit types, this timeout is always suppressed. The setting of this bit has no effect in this case. This bit should not be set during normal operation, but is useful for testing. 0x0
30 R/W Disable Ordering Checks [DOC] Setting this bit to 1 disables the ordering check in the Controller between Completions and Posted requests received from the link. 1'b0
31 R/W Enable Function- Specific Reporting of Type-1 Configuration Accesses [EFSRTCA] Setting this bit to 0 causes all the enabled Functions to report an error when a Type-1 configuration access is received by the Controller, targeted at any Function. Setting it to 1 limits the error reporting to the type-0 Function whose number matches with the Function number specified in the request. If the Function number in the request refers to an unimplemented or disabled Function, all enabled Functions report the error regardless of the setting of this bit. 0x01