Correctable Error Status Register @0x110

This register provides the status of the various correctable errors detected by the PCI Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit position. The states of the bits in the Correctable Error Mask Register have no effect on the status bits of this register. The setting of a correctable error status bit causes the Controller to assert the CORRECTABLE_ERROR_OUT output if the error is not masked in the Correctable Error Mask Register. Header logging of received TLPs does not apply to correctable errors.

Table 1. i_corr_err_status

Bits	SW	Name	Description	Reset
0	R/WOCLR	Receiver Error Status [RES]	This bit is set when an error is detected in the receive side of the Physical Layer of the Controller (e.g., an 8b10b decode error).	0x0
5:1	R	Reserved [R37]	Reserved	0x0
6	R/WOCLR	Bad TP Status [BTS]	This bit is set when an error is detected in a received TLP by the Data Link Layer of the Controller. The conditions causing this error are: an LCRC error, the packet terminates with EDB symbol, but its LCRC field does not equal the inverted value of the calculated CRC.	0x0
7	R/WOCLR	Bad DLLP Status [BDS]	This bit is set when an LCRC error is detected in a received DLLP, and no errors were detected by the Physical Layer.	0x0
8	R/WOCLR	Replay Number Rollover Status [RNRS]	This bit is set when the replay count rolls over after three re-transmissions of a TLP at the Data Link Layer of the Controller.	0x0
11:9	R	Reserved [R38]	Reserved	0x0
12	R/WOCLR	Replay Timer Timeout Status [RTTS]	This bit is set when the replay timer in the Data Link Layer of the Controller times out, causing the Controller to re-transmit a TLP.	0x0
13	R/WOCLR	Advisory Non-Fatal Error Status [ANES]	This bit is set when an uncorrectable error occurs, which is determined to belong to one of the special cases described in the PCI Express Base Specification 2.0. This causes the Controller to assert the CORRECTABLE_ERROR_OUT output in place of NON_FATAL_ERROR_OUT.	0x0
14	R/WOCLR	Corrected Internal Error Status [CIES]	This bit is set when the Controller has detected an internal correctable error condition (a correctable ECC error while reading from any of the RAMs). This bit is also set in response to the client signaling an internal error through the input CORRECTABLE_ERROR_IN.	0x0
15	R/WOCLR	Header Log Overflow Status [HLOS]	This bit is set on a Header Log Register overflow, that is, when the header could not be logged in the Header Log Register because it is occupied by a previous header.	0x0
31:16	R	Reserved [R39]	Reserved	0x0