Lane Margining at Receiver Local Control Register @0xcd8

The Lane Margining at Receiver local control fields are implemented in this Register.

Table 1. i_margining_local_control_reg
Bits SW Name Description Reset
0 R/W Margining Soft Reset [MSR] This bit can be used to reset the Margining internal registers and Margining state machines in the Controller. When asserted:
  1. The State machines will be reset to their default values.
  2. All internal FIFOs will be cleared.
  3. All the P2M and M2P registers will be reset.
  4. This does not reset the Margining Configuration and Management Registers.
Margining Status register will show the last recorded status. This bit will automatically self-clear after 32-CORE_CLK cycles.		 0x0
1 R/W Accept Margining Command Non-Gen4 [AMCNG4] By default, the Controller will process a Margin Command only if it is received while in 16GT/ s L0 State. If a Margin Command is received when the link is not in Gen4-L0 state, then the command will be ignored. If this bit is set, then the Controller accepts and stores a margin command that is received when not in Gen4 L0 state. This command will be processed when the link reaches Gen4 L0 state. 0x0
2 R/W Disable Margin Status Update On Sample Count [DMSUSC] By default, when a Step Margin command is received, the Controller will update Lane Margin status to Margining in Progress when an Error Count update or a Sample Count update is received from PHY. Set this bit to 1 to not update Lane Margin Status on a Sample Count update from PHY. 0x0
3 R/W Enable Step Margin Status Update During Clear Error Log Command [ESMSUCE]
  • 0: (Default Value) When a Clear Error Log Command is received after a Step Margin Command, the Controller will process the Clear Error Log and respond with Clear Error Log Status. The Step Margin command is still active in the PHY. However, the Step Margin status willnot be reflected in the Margin Status Register since the Margin Control Register holds Clear Error Log Command. Host Margining SW needs to configure the Step Margin Command again in order to get the Step Margin Status.
  • 1: When this bit is set to1, the Controller waits for Host SW to read the Clear Error Log Status through a CfgRd. After the Host read the Clear Error Log status, the Controller updates the latest Step Margin Status on to the Margin Status Register while the Margin Control Register holds Clear Error Log Command.
 0x0
28:4 R Reserved [RES] Reserved 0x0
31:29 R/W Write Ack Wait Timer Control [WAWTC] When a WriteCommitted command is issued by the Controller, the PHY must respond with a Write_Ack response. The time for which the Controller waits before timing out is controlled by this register.
  • 000: 10 μs
  • 001: 100 μs
  • 010: 1 ms
  • 011: 2 ms
  • 100: 10 ms (default)
  • 101: 20 ms
  • 110: 100 ms
  • 111: No Timeout
 3'd4