Power Management Control/Status Report @0x84

This location contains the Power Management Control/Status and Data Registers.

Table 1. i_pwr_mgmt_ctrl_stat_rep

Bits	SW	Name	Description	Reset
1:0	R/W	Power State [PS]	This field can also be read or written from the local management APBbus.	0x0
2	R	Reserved [R4]	Reserved	0x0
3	R	No Soft Reset [NSR]	This bit is set to 1 by default. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.	0x01
7:4	R	Reserved [R3]	Reserved	0x0
8	R/W	PME Enable [PE]	This bit can be set or cleared from the local management APB bus by writing a 1 or 0, respectively.	0x0
14:9	R	Reserved [R2]	Reserved	0x0
15	R/WOCLR	PME Status [PMES]	This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.	0x0
23:16	R	Reserved [R1]	Reserved	0x0
31:24	R	Data Register [DR]	This optional register is not implemented in the PCIe Controller. This field is hardwired to 0.	0x0