Gen 3 Link Equalization Debug Register 0x38c
This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN3 Link Equalization. When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen3 Equalization Phase 3. The value in these registers is valid only after link has reached Gen3 L0 state (i.e., only after Gen3 Equalization is completed). The actual value read out will be based on the equalization and can vary based on the equalization process. When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen3 Equalization Phase 2.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 3:0 | R | Link Equalization TX Preset [LEQTXPR] | TX Preset agreed upon for this lane. | 0x0 |
| 4 | R | Link Equalization TX Preset Valid [LEQTXPRV] | TX Preset Valid Indicator. This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2. | 0x0 |
| 7:5 | R | Reserved [RES75] | Reserved | 0x0 |
| 25:8 | R | Link Equalization TX Coefficient [LEQTXCO] | TX Coefficients agreed upon for this lane.
|
0x00000 |
| 31:26 | R | Reserved [RES3126] | Reserved | 0x0 |