Low Power Debug and Control Register 0 @0xc88

This register controls internal behavior of controller for low power operations. Adjustment of this register is not required for normal operations.

Table 1. low_power_debug_and_control0

Bits	SW	Name	Description	Reset
23:0	R/W	L1 substate entry delay [L1XDELAY]	Normaly L1 substate entry process is initiated immedaitely after LTSSM enters L1. A delay in micro-seconds can be given in this field todelay L1 substate entry process. This timeout has 0-1 μs margin of error.	0x0
24	R/W	Do Not block Request interface [L1DBRI]	Before entering L1, controller internally blocks all TLP and Register Request interface entering controller. interfaces are internally unblocked while exiting L1. This field control this behavior. '1' in this field makes the controler to do not perform any blocking to interfaces. '0' makes the controller behaves normaly. This is required onlyfor debug purpose. Power shutoff feature has to be disabled while using this field.	0x0
26:25	R	L1 entry mode [L1EM]	This field shows the last entered L1 mode. This is useful for debug. Bit 0 - Entry mode was ASPM. Bit 1 - Entry mode was PM. This is reset before any new L1 entry.	0x0
27	R/W	Disable L1 exit upon Pending Tlps [L1DLEUP]	Pending Tlps trigger a L1 exit by default. This includes internaly generated messages and internaly blocked TLPs. Setting this bit changes the default behavior. This is required only for debug purpose.	0x0
31:28	R	RSVD	RSVD	4'h0