MSI Mask Cleared Status 2 Register @0xd20
This status register has one bit per function. Each function has a 32-bit MSI Mask. If any bit in the function's MSI Mask register is configured from 1 to 0, then the corresponding function's status bit in this register is set. Local Firmware needs to clear this register by writing a 1.
Each VF has a 32-bit MSI Mask. Each bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. When the status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked inlocal_intrpt_mask_2_reg. Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/WOCLR | VF28 MSI Mask Cleared Status [VF28MSIMSKCLST] | This status bit is set when any of the 32-bits in VF28 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 1 | R/WOCLR | VF29 MSI Mask Cleared Status [VF29MSIMSKCLST] | This status bit is set when any of the 32-bits in VF29 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 2 | R/WOCLR | VF30 MSI Mask Cleared Status [VF30MSIMSKCLST] | This status bit is set when any of the 32-bits in VF30 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 3 | R/WOCLR | VF31 MSI Mask Cleared Status [VF31MSIMSKCLST] | This status bit is set when any of the 32-bits in VF31 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 4 | R/WOCLR | VF32 MSI Mask Cleared Status [VF32MSIMSKCLST] | This status bit is set when any of the 32-bits in VF32 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 5 | R/WOCLR | VF33 MSIMask Cleared Status [VF33MSIMSK] | This status bit is set when any of the 32-bits in VF33 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 6 | R/WOCLR | VF34 MSI Mask Cleared Status [VF34MSIMSKCLST] | This status bit is set when any of the 32-bits in VF34 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 7 | R/WOCLR | VF35 MSI Mask Cleared Status [VF35MSIMSKCLST] | This status bit is set when any of the 32-bits in VF35 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 8 | R/WOCLR | VF36 MSI Mask Cleared Status [VF36MSIMSKCLST] | This status bit is set when any of the 32-bits in VF36 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 9 | R/WOCLR | VF37 MSI Mask Cleared Status [VF37MSIMSKCLST] | This status bit is set when any of the 32-bits in VF37 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 10 | R/WOCLR | VF38 MSI Mask Cleared Status [VF38MSIMSKCLST] | This status bit is set when any of the 32-bits in VF38 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 11 | R/WOCLR | VF39 MSI Mask Cleared Status [VF39MSIMSKCLST] | This status bit is set when any of the 32-bits in VF39 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 12 | R/WOCLR | VF40 MSI Mask Cleared Status [VF40MSIMSKCLST] | This status bit is set when any of the 32-bits in VF40 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 13 | R/WOCLR | VF41 MSI Mask Cleared Status [VF41MSIMSKCLST] | This status bit is set when any of the 32-bits in VF41 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 14 | R/WOCLR | VF42 MSI Mask Cleared Status [VF42MSIMSKCLST] | This status bit is set when any of the 32-bits in VF42 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 15 | R/WOCLR | VF43 MSI Mask Cleared Status [VF43MSIMSKCLST] | This status bit is set when any of the 32-bits in VF43 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 16 | R/WOCLR | VF44 MSI Mask Cleared Status [VF44MSIMSKCLST] | This status bit is set when any of the 32-bits in VF44 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 17 | R/WOCLR | VF45 MSI Mask Cleared Status [VF45MSIMSKCLST] | This status bit is set when any of the 32-bits in VF45 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 18 | R/WOCLR | VF46 MSI Mask Cleared Status [VF46MSIMSKCLST] | This status bit is set when any of the 32-bits in VF46 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 19 | R/WOCLR | VF47 MSI Mask Cleared Status [VF47MSIMSKCLST] | This status bit is set when any of the 32-bits in VF47 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 20 | R/WOCLR | VF48 MSI Mask Cleared Status [VF48MSIMSKCLST] | This status bit is set when any of the 32-bits in VF48 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 21 | R/WOCLR | VF49 MSI Mask Cleared Status [VF49MSIMSKCLST] | This status bit is set when any of the 32-bits in VF49 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 22 | R/WOCLR | VF50 MSI Mask Cleared Status [VF50MSIMSKCLST] | This status bit is set when any of the 32-bits in VF50 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 23 | R/WOCLR | VF51 MSI Mask Cleared Status [VF51MSIMSKCLST] | This status bit is set when any of the 32-bits in VF51 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 24 | R/WOCLR | VF52 MSI Mask Cleared Status [VF52MSIMSKCLST] | This status bit is set when any of the 32-bits in VF52 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 25 | R/WOCLR | VF53 MSI Mask Cleared Status [VF53MSIMSKCLST] | This status bit is set when any of the 32-bits in VF53 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 26 | R/WOCLR | VF54 MSI Mask Cleared Status [VF54MSIMSKCLST] | This status bit is set when any of the 32-bits in VF54 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 27 | R/WOCLR | VF55 MSI Mask Cleared Status [VF55MSIMSKCLST] | This status bit is set when any of the 32-bits in VF55 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 28 | R/WOCLR | VF56 MSI Mask Cleared Status [VF56MSIMSKCLST] | This status bit is set when any of the 32-bits in VF56 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 29 | R/WOCLR | VF57 MSI Mask Cleared Status [VF57MSIMSKCLST] | This status bit is set when any of the 32-bits in VF57 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 30 | R/WOCLR | VF58 MSI Mask Cleared Status [VF58MSIMSKCLST] | This status bit is set when any of the 32-bits in VF58 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |
| 31 | R/WOCLR | VF59 MSI Mask Cleared Status [VF59MSIMSKCLST] | This status bit is set when any of the 32-bits in VF59 MSI Mask is programmed or configured from 1 to 0 by Local Firmware or Host SW. | 0x0 |