L1 PM Substates Capabilities Register @0x904
This register advertises the L1 PM Substates Capabilities.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | PML1.2 Supported [L1PML12SUPP] | When Set this bit indicates that PCI-PM L1.2 is supported. | 0x1 |
| 1 | R | PML1.1 Supported [L1PML11SUPP] | When Set this bit indicates that PCI-PM L1.1 is supported. | 0x1 |
| 2 | R | ASPML1.2 Supported [L1ASPML12SUPP] | When Set this bit indicates that ASPM L1.2 is supported. | 0x1 |
| 3 | R | ASPML1.1 Supported [L1ASPML11SUPP] | When Set this bit indicates that ASPM L1.1 is supported. | 0x1 |
| 4 | R | L1 PM Substates Supported [L1PMSUPP] | When Set this bit indicates that this Port supports L1 PM Substates. | 0x1 |
| 7:5 | R | RSVD | RSVD | 3'h0 |
| 15:8 | R | Port Common Mode Restore Time [L1PrtCmMdReStrTime] | Time (in us) required for this Port to re-establish common mode during exit from PM or ASPM L1.2 substate. | 8'hff |
| 17:16 | R | Port Power-On Time Scale [L1PrtPvrOnScale] | Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of Values: 00b = 2us, 01b = 10us, 10b = 100us, 11b = Reserved Default value is 00. | 0x0 |
| 18 | R | RSVD | RSVD | 1'h0 |
| 23:19 | R | Port Power-On Time Value [R0] | Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. T Power On is the minimum amount of time that each component must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. This is to ensure no device is ever actively driving into an unpowered component. | 0xd |
| 31:24 | R | RSVD | RSVD | 8'h00 |