MSI Mask Cleared Status 1 Register @0xd10
This status register has one bit per function. Each function has a 32-bit MSI Mask. If any bit in the function's MSI Mask register is configured from 1 to 0, then the corresponding function's status bit in this register is set. Local Firmware needs to clear this register by writing a 1.
When each status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked inlocal_intrpt_mask_2_reg . Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/WOCLR | PF0 MSI Mask Cleared Status [PF0MSIMSKCLST] | Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF0 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 1 | R/WOCLR | PF1 MSI Mask Cleared Status [PF1MSIMSKCLST] | Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF1 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enablebit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 2 | R/WOCLR | PF2 MSI Mask Cleared Status [PF2MSIMSKCLST] | Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF2 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 3 | R/WOCLR | PF3 MSI Mask Cleared Status [PF3MSIMSKCLST] | Each PF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in PF3 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enablebit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 4 | R/WOCLR | VF0 MSI Mask Cleared Status [VF0MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF0 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 5 | R/WOCLR | VF1 MSI Mask Cleared Status [VF1MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF1 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 6 | R/WOCLR | VF2 MSI Mask Cleared Status [VF2MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF2 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 7 | R/WOCLR | VF3 MSI Mask Cleared Status [VF3MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF3 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only whenthe MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 8 | R/WOCLR | VF4 MSI Mask Cleared Status [VF4MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF4 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 9 | R/WOCLR | VF5 MSI Mask Cleared Status [VF5MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF5 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 10 | R/WOCLR | VF6 MSI Mask Cleared Status [VF6MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF6 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 11 | R/WOCLR | VF7 MSI Mask Cleared Status [VF7MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF7 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 12 | R/WOCLR | VF8 MSI Mask Cleared Status [VF8MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF8 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only whenthe MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 13 | R/WOCLR | VF9 MSI Mask Cleared Status [VF9MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF9 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 14 | R/WOCLR | VF10 MSI Mask Cleared Status [VF10MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF10 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 15 | R/WOCLR | VF11 MSI Mask Cleared Status [VF11MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF11 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 16 | R/WOCLR | VF12 MSI Mask Cleared Status [VF12MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF12 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 17 | R/WOCLR | VF13 MSI Mask Cleared Status [VF13MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF13 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 18 | R/WOCLR | VF14 MSI Mask Cleared Status [VF14MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF14 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 19 | R/WOCLR | VF15 MSI Mask Cleared Status [VF15MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF15 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 20 | R/WOCLR | VF16 MSI Mask Cleared Status [VF16MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF16 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 21 | R/WOCLR | VF17 MSI Mask Cleared Status [VF17MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF17 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 22 | R/WOCLR | VF18 MSI Mask Cleared Status [VF18MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF18 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 23 | R/WOCLR | VF19 MSI Mask Cleared Status [VF19MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF19 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 24 | R/WOCLR | VF20 MSI Mask Cleared Status [VF20MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF20 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 25 | R/WOCLR | VF21 MSI Mask Cleared Status [VF21MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF21 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 26 | R/WOCLR | VF22 MSI Mask Cleared Status [VF22MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF22 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 27 | R/WOCLR | VF23 MSI Mask Cleared Status [VF23MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF23 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 28 | R/WOCLR | VF24 MSI Mask Cleared Status [VF24MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF24 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 29 | R/WOCLR | VF25 MSI Mask Cleared Status [VF25MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF25 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 30 | R/WOCLR | VF26 MSI Mask Cleared Status [VF26MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF26 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |
| 31 | R/WOCLR | VF27 MSI Mask Cleared Status [VF27MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF27 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW. This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. | 0x0 |