AXI Feature Control Register @0xe5c

This register is for the control of AXI Features.

Table 1. i_axi_feature_reg

Bits	SW	Name	Description	Reset
0	R	Reserved [R0]	Reserved	0x0
1	R/W	Block SLVERR Response to AXI forconfiguration requests [SLVERRCTRL]	This bit if set to 1, AXI Slave masks the SLVERR response to be given in case of UR or CRS completion for configuration requests. If this bit is set to 0, UR and CRS completions from the link causes SLVERR at AXI.	0x1
7:2	R	Reserved [R7]	Reserved	0x0
16:8	R	Reserved [R16]	Reserved	0x0
30:17	R	Reserved [R30]	Reserved	0x0
31	R	Reserved [R31]	Reserved	0x0