LTSSM Transition Debug Control Register67 @0xf9c

This register enables firmware to program two specific LTSSM state transitions to be detected and optionally paused for firmware control.

Table 1. i_ltssm_transition_debug_ctrl_reg67
Bits SW Name Description Reset
0 R/W LTSSM State Transition 6 Freeze Enable [LST6FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 6 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 6. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 6. LTSSM will continue to next legal state.
 0x0
1 R/W LTSSM State Transition 6 Check Enable [LST6CHEN] This bit enables the LTSSM transition 4 check.
  • 1: LTSSM State transition 6 check is enabled.
  • 0: LTSSM State transition 6 check is disabled.
 0x0
8:2 R/W Current LTSSM State 6 [CLTST6] This is the 7-bit Current LTSSM State of LTSSM transition6 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
15:9 R/W Previous LTSSM State 6 [PLTST6] This is the 7-bit Previous LTSSM State of LTSSM transition6 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
16 R/W LTSSM State Transition 7 Freeze Enable [LST7FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 7 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 7. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 7. LTSSM will continue to next legal state.
0x0
17 R/W LTSSM State Transition 7 Check Enable [LST7CHEN] This bit enables the LTSSM transition 1 check.
  • 1: LTSSM State transition 7 check is enabled.
  • 0: LTSSM State transition 7 check is disabled.
 0x0
24:18 R/W Current LTSSM State 7 [CLTST7] This is the 7-bit Current LTSSM State of LTSSM transition7 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
31:25 R/W Previous LTSSM State 7 [PLTST7] This is the 7-bit Previous LTSSM State of LTSSM transition7 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0