PCI Express Device Control and Status Register @0xc8
This register contains control and status bits associated with the device implementing this Function. All the read-write bits in this register can also be written from the local management bus. Likewise, bits designated as RW1C can also be cleared by writing a 1 from the local management bus.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/W | Enable Correctable Error Reporting [ECER] | Enables the sending of ERR_COR messages by the Controller on the detection of correctable errors. | 0x0 |
| 1 | R/W | Enable Non- Fatal Error Reporting [ENFER] | Enables the sending of ERR_NONFATAL messages by the Controller on the detection of non-fatal errors. | 0x0 |
| 2 | R/W | Enable Fatal Error Reporting [EFER] | Enables the sending of ERR_FATAL messages by the Controller on the detection of fatal errors. | 0x0 |
| 3 | R/W | Enable Unsupported Request Reporting [EURR] | Enables the sending of error messages by the Controller on receiving unsupported requests. | 0x0 |
| 4 | R/W | Enable Relaxed Ordering [ERO] | When set, this bit indicates that the device is allowed to set the Relaxed Ordering bit in the Attributes field of transactions initiated from it when the transactions do not require Strong Ordering. | 0x01 |
| 7:5 | R/W | Max Payload Size [MPS] | Specifies the maximum TLP payload size configured. The device must be able to receive a TLP of this maximum size and should not generate TLPs larger than this value. The configuration program sets this field based on the maximum payload size in the Device Capabilities Register and the capability of the other side. | 0x0 |
| 8 | R/W | Extended Tag Field Enable [ETFE] | Enables the extension of the tag field from 5 to 8 bits. | 0x1 |
| 9 | R | Enable Phantom Functions [EPH] | This field is hardwired to 0 as the Controller does not support this feature. | 0x0 |
| 10 | R | Enable Aux Power [EAP] | Used only when device used aux power. This field is hardwired to 0. | 0x0 |
| 11 | R/W | Enable No Snoop [ENS] | When set to 1, the device is allowed to set the No Snoop bit in initiated transactions in which cache coherency is not needed. | 0x1 |
| 14:12 | R/W | Max Read Request Size [MRRS] | Specifies the maximum size allowed in read requests generated by the device. | 0x02 |
| 15 | R/W | Function-Level Reset [FLR] | Writing a 1 into this bit position generates a Function-Level Reset for the selected Function. This bit reads as 0. | 0x0 |
| 16 | R/WOCLR | Correctable Error Detected [CED] | Set to 1 by the Controller when it detects a correctable error, regardless of whether error reporting is enabled or not, and regardless of whether the error is masked. | 0x0 |
| 17 | R/WOCLR | Non-Fatal Error Detected [NFED] | Set to 1 by the Controller when it detects a non-fatal error, regardless of whether error reporting is enabled or not, and regardless of whether the error is masked. | 0x0 |
| 18 | R/WOCLR | Fatal Error Detected [FED] | Set to 1 by the Controller when it detects a fatal error, regardless of whether error reporting is enabled or not, and regardless of whether the error is masked. | 0x0 |
| 19 | R/WOCLR | Unsupported Request Detected [URD] | Set to 1 by the Controller when it receives an unsupported request, regardless of whether its reporting is enabled or not. | 0x0 |
| 20 | R | Aux Power Detected [APD] | Set when auxiliary power is detected by the device. This is an unused field. | 0x0 |
| 21 | R | Transaction Pending [TP] | Indicates if any of the Non-Posted requests issued by the Function are still pending. | 0x0 |
| 31:22 | R | Reserved [R4] | Reserved | 0x0 |