DPA Capability Register @0x1c4
This register contains the DPA capability parameters for the associated Function.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 4:0 | R | Maximum Number of Substates [MNS] | Maximum number of DPA substates supported by the Function (the value in this field is the number of substates minus 1). | 5'd7 |
| 7:5 | R | Reserved [R0] | Reserved | 0x0 |
| 9:8 | R | Transition Latency Unit [TLU] | This is the unit of the transition latencies specified in the Transition Latency Value 0 and Transition Latency Value 1 fields of this register (00 = 1 ms, 01 = 10 ms, 10 = 100 ms, 11 = reserved). | 0x0 |
| 11:10 | R | Reserved [R1] | Reserved | 0x0 |
| 13:12 | R | Power Allocation Scale [PAS] | This is the scale used to compute the actual power from the values specified in the Dynamic Power Allocation Array Registers 0 - 7. The actual power in Watts is obtained by multiplying the value in the Dynamic Power Allocation Array Register by this scale factor (00 = 10x, 01 = 1x, 10 = 0.1x, 11 = 0.01x). | 0x0 |
| 15:14 | R | Reserved [R2] | Reserved | 0x0 |
| 23:16 | R | Transition Latency Value 0 [TLV0] | Specifies the transition latency for the substate. Each of the 32 substates may specify one of the two transition latency values. This field contains the first of the two latency values. The unit of latency is specified by the Transition Latency Unit field of this register. | 8'h10 |
| 31:24 | R | Transition Latency Value 1 [TLV1] | Specifies the second of the two transition latency values for the substates. The unit of latency is specified by the Transition Latency Unit field of this register. | 8'h8 |