L0S Timeout Limit Register @0x24
This register defines the timeout value for transitioning to the L0S power state. If the transmit side has been idle for this interval, the Controller will transmit the idle sequence on the link and transition the state of the link to L0S .
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 15:0 | R/W | L0S Timeout [LT] | Contains the timeout value (in units of 16 ns) for transitioning to the L0S power state. Setting this parameter to 0 permanently disables the transition to the L0S power state. | 0x0177 |
| 31:16 | R | Reserved [R4] | Reserved | 0x0 |