Physical Layer 16GTs Status Register @0x9cc
Physical Layer 16GTs Status Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | Equalization 16.0 GT/s Complete [EQC16] | This bit, when set to 1, indicates that the Transmitter Equalization procedure has completed for 16.0 GT/s. STICKY. | 0x0 |
| 1 | R | Equalization 16.0 GT/s Phase 1 Successful [EP1S16] | This bit, when set to 1, indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY. | 0x0 |
| 2 | R | Equalization 16.0 GT/s Phase 2 Successful [EP2S16] | This bit, when set to 1, indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY. | 0x0 |
| 3 | R | Equalization 16.0 GT/s Phase 3 Successful [EP3S16] | This bit, when set to 1, indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY. | 0x0 |
| 4 | R/WOCLR | Link Equalization Request 16.0 GT/s [LE16] | When the Controller (RP) receives an 16GTs equalization request from an Upstream Port the Controller internally sets this bit to 1 (i.e., when RP is in the Recovery.RcvrCfg state and receives eight consecutive TS2 Ordered Sets with the Request Equalization bit set to 1b). The LOCAL_INTERRUPT output is also asserted if Link Equalization Request Interrupt Enable is enabled. | 0x0 |
| 31:5 | R | R0 | Reserved | 0x0 |