SR-IOV Capabilities Register @0x204
This register defines various capabilities of the SR-IOV implementation.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | VF Migration Capable [VFMC] | Set when the Controller supports VF migration. Hardwired to 0. | 0x0 |
| 1 | R | ARI Capable Hierarchy Preserved [ACHP] | A 1 in this bit position indicates that the ARI Capable Hierarchy bit in the SR-IOV Control Register is preserved across certain power state transitions (see the PCI SIG Single Root I/O Virtualization and Sharing Specifications, Version 1.1, Section 3.3.3.5 for details). This bit is set to 1 by default, but can be modified from the local management bus. | 0x1 |
| 2 | R | VF 10-Bit Tag Requester supported. [VFT10RS] | If set all VFs associated with this PF supports 1-bit requester capability; otherwise, the VF does not. This bit can be disabled using local management register. | 0x0 |
| 31:3 | R | RSVD | RSVD | 29'h00000000 |