Slot Control and Status Register @0xd8

This register contains control bits specific to PCI Express slot parameters and status bits specific to the PCI Express Slot. All the read-write bits in this register can also be written from the local management APB bus.

Table 1. i_slot_ctrl_status
Bits SW Name Description Reset
0 R/W Attention Button Pressed Enable [ABPE] When Set to 1b, this bit enables software notification on an attention button pressed event. If the Attention Button Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. 1'b0
1 R/W Power Fault Detected Enable [PFDE] When Set, this bit enables software notification on a power fault event If a Power Controller that supports power fault detection is not implemented, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. 1'b0
2 R/W MRL Sensor Changed Enable [MSCE] When Set, this bit enables software notification on a MRL sensor changed event If the MRL Sensor Present bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. 1'b0
3 R/W Presence Detect Changed Enable [PDCE] When Set, this bit enables software notification on a presence detect changed event. If the Hot-Plug Capable bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. 1'b0
4 R/W Command Completed Interrupt Enable [CCIE] If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b), when Set, this bit enables software notification when a hot- plug command is completed by the Hot-Plug Controller. If Command Completed notification is not supported, this bit must be hardwired to 0b. Default value of this bit is 0b. 1'b0
5 R/W Hot-Plug Interrupt Enable [HPIE] When Set, this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. 1'b0
7:6 R/W Attention Indicator Control [AIC] If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write. Defined encodings are:
  • 00b Reserved
  • 01b On
  • 10b Blink
  • 11b Off
 2'b11
9:8 R/W Power Indicator Control [PIC] If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write. Defined encodings are:
  • 00b Reserved
  • 01b On
  • 10b Blink
  • 11b Off
 2'b11
10 R/W Power Controller Control [PCC] If a Power Controller is implemented, this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write, if required to, without waiting for the previous command to complete in which case the read value is undefined. The defined encodings are:
  • 0b Power On
  • 1b Power Off
 1'b1
11 R Electromechanic Interlock Control [EMIC] If an Electromechanical Interlock is implemented, a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit always returns a 0b. 1'b0
12 R/W Data Link Layer State Changed Enable [DLLSCE] If the Data Link Layer Link Active Reporting capability is 1b, this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active Reporting Capable bit is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. 1'b0
15:13 R Reserved [RSCS1] Reserved 0x0
16 R/WOCLR Attention Button Pressed [ABPRSD] If an Attention Button is implemented, this bit is Set when the attention button is pressed. If an Attention Button is not supported, this bit must not be Set. 0x0
17 R/WOCLR Power Fault Detected [PFD] If a Power Controller that supports power fault detection is implemented, this bit is Set when the Power Controller detects a power fault at this slot. Note that, depending on hardware capability, it is possible that a power fault can be detected at any time, independent of the Power Controller Control setting or the occupancy of the slot. If power fault detection is not supported, this bit must not be Set. 0x0
18 R/WOCLR MRL Sensor Changed [MRLSC] If an MRL sensor is implemented, this bit is Set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be Set. 0x0
19 R/WOCLR Presence Detect Changed [PDC] This bit is set when the value reported in the Presence Detect State bit is changed. 0x0
20 R/WOCLR Command Completed [CMDCMPL] If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b), this bit is Set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command. The Command Completed status bit is Set as an indication to host software that the Hot-Plug Controller has processed the previous command and is ready to receive the next command; it provides no guarantee that the action corresponding to the command is complete. If Command Completed notification is not supported, this bit must be hardwired to 0b. 0x0
21 R MRL Sensor State [MRLSS] This bit reports the status of the MRL sensor if implemented. Defined encodings are:
  • 0b MRL Closed
  • 1b MRL Open
 1'b1
22 R Presence Detect State [PDS] This bit indicates the presence of an adapter in the slot, reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. Note that the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. Consequently, form factors that require a power controller for hot-plug must implement a physical pin presence detect mechanism. Defined encodings are:
  • 0b Slot Empty
  • 1b Card Present in slot
 0x0
23 R Electromechanic Interlock Status [EMIS] If an Electromechanical Interlock is implemented, this bit indicates the status of the Electromechanical Interlock. Defined encodings are:
  • 0b Electromechanical Interlock Disengaged
  • 1b Electromechanical Interlock Engaged
 0x0
24 R/WOCLR Data Link Layer State Changed [DLLSC] This bit is Set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event, software must read the Data Link Layer Link Active bit of the Link Status register to determine if the Link is active before initiating configuration cycles to the hot plugged device. 0x0
31:25 R Reserved [RSCS2] Reserved 0x0