Revision ID and Class Code Register @0x8
This register contains the Revision ID and Class Code associated with the device incorporating the PCIe core.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R | Revision ID [RID] | Assigned by the manufacturer of the device to identify the revision RO setting of this field. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. | 8'h0 |
| 15:8 | R | Programming Interface Byte [PIB] | Identifies the register set layout of the device. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. | 0x0 |
| 23:16 | R | Sub-Class Code [SCC] | Identifies a sub-category within the selected function. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. | 8'h0 |
| 31:24 | R | Class Code [CC] | Identifies the function of the device. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. | 8'h0 |