Gen 3 Gen4 Link Equalization 2ms Timeout Tuning Register @0x364

This register is used to tune the time spent for evaluation per TX Setting in Endpoint Phase 2 (RC Mode Phase 3) of GEN3, GEN4 Link Equalization. The PCIe Spec defines a timeout of 2ms per TX setting and hence the default value for this register is set to 2ms. This can be tweaked based on the total number of iterations done and the time required for the PHY to respond with feedback for RXEQEVAL request. The total time taken in Endpoint Phase 2 (RC Mode Phase 3) must be less than 24 ms as defined by spec. Guideline: (Total Number of iterations)*(link_eq_timeout_2ms_reg + max time required for PHY to respond to RXEQEVAL) less than 24ms

Table 1. i_gen3_gen4_link_eq_timeout_2ms_reg
Bits SW Name Description Reset
27:0 R/W Link Equalization Timeout 2ms [LEQT2ms] Time spent for evaluation per TX Setting in Endpoint Phase 2 (RC Mode Phase 3) of Link Equalization specified in multiples of 16ns. For example: The value 125000 will result in 125000*16ns = 2ms. Simulation with reduced time mode (PCIE_SIM define) will give a smaller value of 300 as power on reset value. 0x1E880
28 R Reserved [R28] Reserved 0x0
29 R/W RXEQINPROGRESS Abort Disable [RXEQABD] In an unexpected case where the PIPE_PCLK stops due to error in equalization, this bit can be set to de-couple RxEqInProgress from the rest of the equalization state machine. This bit should not be set for normal usage. 0x0
31:30 R/W RXEQINPROGRESS Abort Timer Mode Control [RXEQABM] When a 24 ms timeout occurs in the LTSSM Equalization Phase 2 (EP Mode) or Phase 3 (RP Mode), the Controller aborts Equalization Phase 2 (EP Mode)/Phase 3 (RP Mode) and transitions to Recovery.Speed. In this case, theRxEqEval output on the PIPE Interface will be de-asserted immediately (if it was asserted). The RxEqInProgress output will stay high and waits for PhyStatus pulse. Controller implements a timer to select an upper limit to wait for this PhyStatus pulse during an abort to de-assert RxEqInProgress.
  • 00: Wait for a maximum of 4 PIPE_PCLK period.
  • 01: Wait for a maximum of 8 PIPE_PCLK period.
  • 10: Wait for a maximum of 16 PIPE_PCLK period.
  • 11: Disabled.
Wait until PhyStatus Pulse is received.
Note: This register is used only if RxEqEval was asserted when LTSSM 24ms timeout occured in Equalization.
 0x3