L1 PM Substates Control 1 Register @0x908

This register is used to Control ASPM, PCI PM L1 substates.

Table 1. i_L1_PM_ctrl_1
Bits SW Name Description Reset
0 R/W PML1.2 Enable [L1PML12EN] When Set this bit enables PCI-PM L1.2. 0x0
1 R/W PML1.1 Enable [L1PML11EN] When Set this bit enables PCI-PM L1.1. 0x0
2 R/W ASPML1.2 Enable [L1ASPML12EN] When Set this bit enables ASPM L1.2. 0x0
3 R/W ASPML1.1 Enable [L1ASPML11EN] When Set this bit enables ASPM L1.1. 0x0
7:4 R RSVD RSVD 4'h0
15:8 R Common Mode Restore Time [L1CmMdReStrTime] This field is reserved for EP. 0x0
25:16 R/W LTR L1.2 Threshold Value [L1ThrshldVal] Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). 0x0
28:26 R RSVD RSVD 3'h0
31:29 R/W LTR L1.2 Threshold Scale [L1ThrshldSc] This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.
  • 000 - Value times 1 ns
  • 001 - Value times 32 ns
  • 010 - Value times 1024 ns
  • 011 - Value times 32,768 ns
  • 100 - Value times 1,048,576 ns
  • 101 - Value times 33,554,422 ns
  • 110–111 - Not permitted
 0x0